David C Patrick

US Patent:

20130187956, Jul 25, 2013

Filed:

Jan 23, 2012

Appl. No.:

13/356551

Inventors:

Walter R. STEINER - Flagler Beach FL, US
Eric LUM - San Jose CA, US
Dale L. KIRKLAND - Madison AL, US
Steven James HEINRICH - Madison AL, US
David Charles PATRICK - Madison AL, US

International Classification:

G09G 5/00

US Classification:

345660

Abstract:

In a graphics processing pipeline, a processing unit establishes a bounding box around a polygon in order to identify sample points that are covered by the polygon. For a given sample point included within the bounding box, the processing unit constructs a set of lines that intersect at the sample point, where each line in the set of lines is parallel to at least one side of the polygon. When all vertices of the polygon reside on one side of at least one line in the set of lines, the processing unit may reduce the size of the bounding box to exclude the sample point.

US Patent:

20140011859, Jan 9, 2014

Filed:

Jan 20, 2011

Appl. No.:

13/574398

Inventors:

Eric N. Olson - Dallas TX, US
David Patrick - Dallas TX, US

Assignee:

Board of Regents, The University of Texas System - Austin TX

International Classification:

C12N 15/113

US Classification:

514 44 A

Abstract:

The present invention provides methods of treating diseases and disorders associated with aberrant erythropoiesis. Specifically, the present invention provides a method for treating polycythemia in a subject by administering an inhibitor of miR-451. Methods of increasing red blood cell count and treating anemia in a subject by administering miR-451 mimetics are also disclosed.

US Patent:

6081876, Jun 27, 2000

Filed:

Sep 22, 1997

Appl. No.:

8/935242

Inventors:

Tony M. Brewer - Plano TX
David M. Patrick - Plano TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1214

US Classification:

711163

Abstract:

A computer memory management system that allocates each node's network cache into protected and unprotected regions. Nodes are previously configured into error containment cluster of nodes (ECCNs). Unprotected network caches may encache data accessed from any node's unprotected memory. Protected network caches may encache data accessed from nodes that are within the same ECCN, but only from a node's protected main memory. Memory address allocation techniques known in the art enable the system to know whether a processor's request for data will be found in protected or unprotected memory. Under the present invention, a node is able to first refer to network cache (protected or unprotected, as appropriate) in locating the data. If the data is not in cache, then the system refers to main memory. The present invention thus enables superior memory access advantages of cache memory techniques.

US Patent:

47114746, Dec 8, 1987

Filed:

Oct 21, 1986

Appl. No.:

6/921097

Inventors:

David H. Patrick - Plano TX

Assignee:

Atlantic Richfield Company - Los Angeles CA

International Classification:

F16L 1500

US Classification:

2853323

Abstract:

An improved seal ring comprising a polymeric material ring in combination with a softer polymeric material ring. The seal ring can be used in either male or female fittings and is adapted to seal by mating engagement of the polymeric material with one set of threads and a recess in the other set of threads.

US Patent:

58450718, Dec 1, 1998

Filed:

Sep 27, 1996

Appl. No.:

8/720368

Inventors:

David M. Patrick - Plano TX
Alan D. Gant - Plano TX
David M. Chastain - Plano TX

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1214
G06F 1316

US Classification:

39520045

Abstract:

The multi-node multiprocessor system with globally shared memory is partitioned into groups of nodes called error containment clusters of nodes or ECCNs. The nodes would be partitioned such that an ECCN resides on a column of nodes or a row of nodes. Within each ECCN there is coherent memory sharing. Between the ECCNs, the communication is through a messaging protocol. The memory within each node is also partitioned into protected and unprotected memory. Unprotected memory is used for messaging and protected memory is used for sharing. A failure in an error containment cluster would corrupt the memory within that cluster, specifically the protected memory within that cluster and also the unprotected memory used by that cluster to communicate with the other clusters. However, the other clusters could continue to run because their protected memory would be unaffected, and could continue to communicate through the remaining unprotected memory.

US Patent:

59308222, Jul 27, 1999

Filed:

Sep 27, 1996

Appl. No.:

8/720330

Inventors:

Kenneth Chaney - Plano TX
David M. Chastain - Plano TX
David M. Patrick - Plano TX

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 1318

US Classification:

711150

Abstract:

A method and system of maintaining strong ordering in a multiprocessor computer system having a coherent memory. Memory transactions are send from one or more processors to a processor agent. The processor agent sends the transactions to a memory agent via a crossbar switch. The memory agent performs memory coherency operations and sends memory transactions back to the processor agents via the crossbar switch. The crossbar switch, however, may alter the order in which the memory transactions are forwarded to the processor agent. Therefore, the memory agent also sends a timestamp for each memory transaction directly to the processor agent via a dedicated link. An arbitrator within the processor agent receives the timestamps and the memory transactions. Using the timestamps, the arbitrator reorders the memory transactions and sends the transactions to the processors in the order in which the transactions were sent. In addition, the memory agent sends a parity signal with each timestamp.

US Patent:

20220365848, Nov 17, 2022

Filed:

Jul 27, 2022

Appl. No.:

17/874483

Inventors:

- Boise ID, US
David Patrick - McKinney TX, US

International Classification:

G06F 11/10
G06F 11/30
G06F 12/02
G06F 13/16
G06F 12/0891

Abstract:

Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.

US Patent:

20220350768, Nov 3, 2022

Filed:

Jul 15, 2022

Appl. No.:

17/866130

Inventors:

- Boise ID, US
David Patrick - McKinney TX, US

International Classification:

G06F 13/40
G06F 9/46

Abstract:

A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.

Address:

629 Fall Wheat Dr, Plano, TX 75094

VIN:

5TFRT54177X004336

Make:

TOYOTA

Model:

TUNDRA

Year:

2007