David T Patten

US Patent:

7808258, Oct 5, 2010

Filed:

Jun 26, 2008

Appl. No.:

12/146552

Inventors:

Marc A Mangrum - Manchaca TX, US
Kenneth R Burch - Austin TX, US
David T Patten - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 1/02
G01R 1/073
G01R 31/28

US Classification:

324755, 324765

Abstract:

A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

US Patent:

7262615, Aug 28, 2007

Filed:

Oct 31, 2005

Appl. No.:

11/263089

Inventors:

Edmond Cheng - Cedar Park TX, US
Addi B. Mistry - Austin TX, US
David T. Patten - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/02

US Classification:

324755, 324765

Abstract:

A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.

US Patent:

8044494, Oct 25, 2011

Filed:

Sep 25, 2009

Appl. No.:

12/567469

Inventors:

Addi B. Mistry - Austin TX, US
Marc A. Mangrum - Manchaca TX, US
David T. Patten - Austin TX, US
Jesse Phou - Austin TX, US
Ziep Tran - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/552
H01L 23/02

US Classification:

257659, 257686, 257E23114

Abstract:

A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

US Patent:

20040195591, Oct 7, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/302130

Inventors:

John Gehman - Austin TX, US
Brian Christensen - Dybvad, DK
James Kleffner - Leander TX, US
Addi Mistry - Austin TX, US
David Patten - Austin TX, US
John Rohde - Ega, DK
Daryl Wilde - Austin TX, US

International Classification:

H01L027/10

US Classification:

257/202000

Abstract:

A stacked die system () has a first die () having a first surface with active circuitry, a second die () having a first surface with active circuitry, and a conductive shield () interposed between the first surface of the first die and the first surface of the second die. In one embodiment, the distance between the first surfaces of the first and second die is less than one millimeter. The stacked die system may also include a package substrate () where the active circuitry of the first and second die are electrically connected to the package substrate. The electrical connections may be formed using wire bonds (). Alternatively, the first die may be connected to the package substrate in a flip chip configuration. In one embodiment, the active circuitry of the first die generates RF signals where the shield helps protect the RF signals from interference caused by the active circuitry of the second die.

US Patent:

20070141751, Jun 21, 2007

Filed:

Dec 16, 2005

Appl. No.:

11/311579

Inventors:

Addi Mistry - Austin TX, US
Marc Mangrum - Manchaca TX, US
David Patten - Austin TX, US
Jesse Phou - Austin TX, US
Ziep Tran - Austin TX, US

International Classification:

H01L 21/00

US Classification:

438109000

Abstract:

A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

US Patent:

20080108179, May 8, 2008

Filed:

Jan 3, 2008

Appl. No.:

11/968873

Inventors:

Addi Mistry - Austin TX, US
Marc Mangrum - Manchaca TX, US
David Patten - Austin TX, US
Jesse Phou - Austin TX, US
Ziep Tran - Austin TX, US

Assignee:

Freescale Semiconductor, Inc - Austin TX

International Classification:

H01L 21/56

US Classification:

438117000, 438127000, 257E21502

Abstract:

A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

US Patent:

20220384413, Dec 1, 2022

Filed:

May 25, 2021

Appl. No.:

17/303251

Inventors:

- Edinburgh, GB
Justin Richardson - Edinburgh, GB
Michael Robinson - Edinburgh, GB
David Patten - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H01L 27/02
H01L 23/66
H01L 21/78
H01L 23/498
H03F 3/187
H03F 3/45

Abstract:

A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

US Patent:

20210287841, Sep 16, 2021

Filed:

Feb 11, 2021

Appl. No.:

17/173486

Inventors:

- Edinburgh, GB
David Patten - Austin TX, US
Jun Yan - Austin TX, US

International Classification:

H01F 27/28
H01F 27/24
H01F 17/00

Abstract:

A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform said positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.