David M Paulsen

US Patent:

20200167126, May 28, 2020

Filed:

Nov 28, 2018

Appl. No.:

16/202310

Inventors:

- Armonk NY, US
David Paulsen - Inver Grove Heights MN, US
George Paulik - Rochester MN, US
Karl Erickson - Rochester MN, US
Gregory J. Uhlmann - Rochester MN, US

International Classification:

G06F 7/50

Abstract:

A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2*a unit capacitance (C). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.

US Patent:

20180350941, Dec 6, 2018

Filed:

May 31, 2017

Appl. No.:

15/609814

Inventors:

- Armonk NY, US
David P. PAULSEN - Inver Grove Heights MN, US

International Classification:

H01L 29/66
H01L 29/732
H01L 29/08
H01L 23/00

Abstract:

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

US Patent:

20180350942, Dec 6, 2018

Filed:

Nov 7, 2017

Appl. No.:

15/805210

Inventors:

- Armonk NY, US
David P. PAULSEN - Inver Grove Heights MN, US

International Classification:

H01L 29/66
H01L 29/08
H01L 29/732
H01L 23/00

Abstract:

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.