David Palmer Pease

US Patent:

7129417, Oct 31, 2006

Filed:

Apr 29, 2004

Appl. No.:

10/835464

Inventors:

Todd Arthur Cannon - Rochester MN, US
Benjamin Aaron Fox - Rochester MN, US
Roger John Gravrok - Eau Claire WI, US
Mark Kenneth Hoffmeyer - Rochester MN, US
David Lawrence Pease - Rochester MN, US
Ryan James Schlichting - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1/03

US Classification:

174255, 361803, 361777, 174256

Abstract:

A method and structures are provided for implementing customizable dielectric printed circuit card traces. A void is defined near selected signal traces. The void is then filled with a dielectric material having a predefined dielectric property. The dielectric material is selected to alter at least one predefined electrical property of the selected signal traces, such as, coupling, propagation delay and attenuation. In one embodiment, an outer layer of a printed circuit card includes a plurality of signal traces and a mating circuit card layer including a plurality of matching signal traces is attached to the outer layer of the printed circuit card to create a cavity near selected signal traces. The cavity is filled with the selected dielectric material. In another embodiment, dielectric material is selectively removed near signal traces on an outer layer of the printed circuit card to define a void near selected signal traces.

US Patent:

7131084, Oct 31, 2006

Filed:

Dec 9, 2003

Appl. No.:

10/731064

Inventors:

Todd Arthur Cannon - Rochester MN, US
Roger John Gravrok - Eau Claire WI, US
Mark Owen Maxson - Mantorville MN, US
David Lawrence Pease - Rochester MN, US
Ryan James Schlichting - Rochester MN, US
Patrick Evarist Sobotta - Stewartville MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

716 5, 716 1, 716 2, 716 4, 716 10, 716 15

Abstract:

A method, apparatus and computer program product are provided for implementing automated detection of excess aggressor shape capacitance coupling in printed circuit board layouts. A PCB design file containing an electronic representation of a printed circuit board design is received. A list of candidate shapes is identified. The candidate shapes are disposed on layers adjacent to aggressor planes. A capacitance coupling the candidate shapes to adjacent aggressor planes is calculated. A ratio of the calculated capacitance and a decoupling capacitance connecting the candidate shapes to a reference plane is determined. The PCB design file containing an electronic representation of a printed circuit board design includes shape data and text data that are extracted to produce a list of shapes' names, areas, locations and planes; and includes data defining thickness and relative permittivity of the dielectric layers used for calculating the effective capacitance is an inter-layer parallel-plate effective capacitance.

US Patent:

7197818, Apr 3, 2007

Filed:

Aug 31, 2006

Appl. No.:

11/512961

Inventors:

Todd Arthur Cannon - Rochester MN, US
Benjamin Aaron Fox - Rochester MN, US
Roger John Gravrok - Eau Claire WI, US
Mark Kenneth Hoffmeyer - Rochester MN, US
David Lawrence Pease - Rochester MN, US
Ryan James Schlichting - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 3/36

US Classification:

29830, 29846, 174254, 361761

Abstract:

A method and structures are provided for implementing customizable dielectric printed circuit card traces. A void is defined near selected signal traces. The void is then filled with a dielectric material having a predefined dielectric property. The dielectric material is selected to alter at least one predefined electrical property of the selected signal traces, such as, coupling, propagation delay and attenuation. In one embodiment, an outer layer of a printed circuit card includes a plurality of signal traces and a mating circuit card layer including a plurality of matching signal traces is attached to the outer layer of the printed circuit card to create a cavity near selected signal traces. The cavity is filled with the selected dielectric material. In another embodiment, dielectric material is selectively removed near signal traces on an outer layer of the printed circuit card to define a void near selected signal traces.

US Patent:

7885781, Feb 8, 2011

Filed:

Jul 2, 2008

Appl. No.:

12/166807

Inventors:

Todd A. Cannon - Rochester MN, US
Roger J. Gravrok - Eau Claire WI, US
David L. Pease - Rochester MN, US
Ryan J. Schlichting - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/00
G01R 31/14

US Classification:

702117

Abstract:

Methods, systems, and computer program products are disclosed for acquiring test data from an electronic circuit by mounting a probe adjacent to a capture point on an electronic circuit board, capturing by the probe an electronic signal of the electronic circuit, digitizing by the probe the captured signal, and transmitting by the probe the digitized signal from the probe through a data communications connection to a remote device. Acquiring test data from an electronic circuit also includes storing by the probe the digitized signal in the probe. Acquiring test data from an electronic circuit may include processing by the probe the digitized signal. Acquiring test data from an electronic circuit also may include synchronizing acquisition of test data by the probe with acquisition of test data by one or more other probes.

US Patent:

57676984, Jun 16, 1998

Filed:

Jun 6, 1996

Appl. No.:

8/659293

Inventors:

Roger Dale Emeigh - Rochester MN
James Francis Mikos - Rochester MN
David Lawrence Pease - Rochester MN
James David Strom - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 190175
H03K 19094

US Classification:

326 83

Abstract:

A plurality of high speed differential output drivers are coupled to a reference current generator such that each output driver receives a substantially identical copy of a reference current signal for controlling one or more operational parameters (e. g. , the propagation delay or skew) of the output driver. Multiple copies of the reference current signal are generated within the same region of an integrated circuit chip, thereby minimizing any process variations within the chip that might cause variances between the individual copies of the reference current signal. Each differential output driver has a differential pair of transistors that are coupled to ground or supply voltage through a common mode resistor that controls the common mode component of the driver output independent of the voltage swing of the output.