David L Pedersen

US Patent:

6429029, Aug 6, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/224166

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2166

US Classification:

438 14, 438 10, 438 17

Abstract:

One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die.

US Patent:

6456099, Sep 24, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/224169

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3102

US Classification:

324754, 3241581

Abstract:

One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e. g.

US Patent:

6525555, Feb 25, 2003

Filed:

May 16, 2000

Appl. No.:

09/573489

Inventors:

Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3126

US Classification:

324765, 324754, 324760

Abstract:

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

US Patent:

6534856, Mar 18, 2003

Filed:

Mar 27, 2001

Appl. No.:

09/819143

Inventors:

Benjamin N. Eldridge - Danville CA
Gary W. Grube - Pleasanton CA
Igor Y. Khandros - Orinda CA
Gaetan L. Mathieu - Livermore CA
David V. Pedersen - Scotts Valley CA
Michael A. Stadt - Castro Valley CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2304

US Classification:

257698, 257773, 439 66, 439 68, 439 70, 439 71, 439 72, 439 73

Abstract:

Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.

US Patent:

6551844, Apr 22, 2003

Filed:

Dec 31, 1998

Appl. No.:

09/224673

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2166

US Classification:

438 14, 438 15, 438 17

Abstract:

One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

US Patent:

6597187, Jul 22, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/752902

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3102

US Classification:

324754, 3241581

Abstract:

An integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e. g.

US Patent:

6603324, Aug 5, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/753312

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3102

US Classification:

324755, 324756, 3241581

Abstract:

One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e. g.

US Patent:

6621260, Sep 16, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/752795

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3128

US Classification:

3241581, 361111, 361 56, 361 58

Abstract:

One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e. g.