David R Potts

US Patent:

6844218, Jan 18, 2005

Filed:

Jan 23, 2002

Appl. No.:

10/055445

Inventors:

David J. Potts - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2150
H01L 2166
H01L 2146

US Classification:

438110, 438 14, 438460, 438462

Abstract:

A method of forming a plurality of integrated circuit die on a semiconductor wafer (). The method forms a first integrated circuit die () in a first area in a fixed position relative to the semiconductor wafer, by forming at least two devices () in the first area, the at least two devices selected from a group of active and passive devices, and by forming a first metal layer () comprising portions connecting to the at least two devices in the first area. The method also forms a second integrated circuit die () in a second area in a fixed position relative to the semiconductor wafer, the second area separated from the first area by a scribe area (). The formation of the second integrated circuit die comprises the steps of forming at least two devices () in the second area, the at least two devices selected from a group of active and passive devices, and forming the first metal layer to further comprise portions connecting to the at least two devices in the second area. The method also forms the first metal layer to further comprise a portion electrically connecting a portion of the first metal layer in the first area to a portion of the first metal layer in the second area and thereby extending in the scribe area.