David C Pritchard

US Patent:

6562700, May 13, 2003

Filed:

May 31, 2001

Appl. No.:

09/873043

Inventors:

Sam Gu - Vancouver WA
David Pritchard - Portland OR
Derryl D. J. Allman - Camas WA
Ponce Saopraseuth - Gresham OR
Steve Reder - Boring OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21322

US Classification:

438477, 438710, 438725

Abstract:

A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing the photoresist mask in a plasma reactor to a plasma formed using a reducing gas until the photoresist mask is removed. In a preferred embodiment the reducing gas is selected from the group consisting of NH , H , forming gas, and a mixture of NH and H. The process further provides for the removal of etch residues by first contacting the low k carbon-doped silicon oxide dielectric material with a solvent capable of dissolving and/or removing etch residues left from forming the openings in the low k dielectric material, and from removing the photoresist mask used to form the openings in the low k carbon-doped silicon oxide dielectric material; and then annealing the substrate in an annealing chamber at a temperature sufficient to remove liquid and gaseous byproducts from the low k carbon-doped silicon oxide dielectric material.

US Patent:

7259083, Aug 21, 2007

Filed:

Oct 22, 2004

Appl. No.:

10/971961

Inventors:

Santosh S. Menon - Troutdale OR, US
Hemanshu D. Bhatt - Vancouver WA, US
David Pritchard - Portland OR, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/3205

US Classification:

438586, 438597, 257E21507, 257E21582, 257E2159

Abstract:

The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

US Patent:

7955919, Jun 7, 2011

Filed:

Dec 19, 2007

Appl. No.:

11/960554

Inventors:

David Pritchard - Portland OR, US
Hemanshu Bhatt - Vancouver WA, US
David T. Price - Gresham OR, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/336

US Classification:

438197, 438291, 438301, 257E21429

Abstract:

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

US Patent:

20050191812, Sep 1, 2005

Filed:

Mar 1, 2004

Appl. No.:

10/791337

Inventors:

David Pritchard - Portland OR, US
Hemanshu Bhatt - Vancouver WA, US
David Price - Gresham OR, US

International Classification:

H01L021/336

US Classification:

438299000

Abstract:

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

US Patent:

20130047553, Feb 28, 2013

Filed:

Feb 15, 2012

Appl. No.:

13/397097

Inventors:

Glyn Russell - New City NY, US
Charles Greco - Bardonia NY, US
Lars Wihlborg - Stratford CT, US
Robert J. Coulton - West Milford NJ, US
David Anzini - Middletown NY, US
Brian Ehrhardt - Orangeburg NY, US
Francis Olajide, JR. - Bronx NY, US
Eric Plourde - Frankfort IL, US
David Pritchard - Morris IL, US

Assignee:

ILLINOIS TOOL WORKS INC. - Glenview IL

International Classification:

B65B 61/00

US Classification:

53410

Abstract:

The method and apparatus relates to providing a slit, perforation, line of weakness or similar structure in a flange of a zipper for a reclosable package or bag, including a high-capacity zipper. The slit, perforation, line of weakness or similar structure provides an opening for filling the reclosable package or bag without the need to separate the zipper profiles from each other. After filling, the opening is sealed and the cosmetic appearance of the reclosable package or bag is maintained.

US Patent:

20220285274, Sep 8, 2022

Filed:

Mar 8, 2021

Appl. No.:

17/194565

Inventors:

- Santa Clara CA, US
David Pritchard - Glenville NY, US
Ryan W. Sporer - Mechanicville NY, US
Manjunatha Prabhu - Clifton Park NY, US

International Classification:

H01L 23/535
H01L 27/12
H01L 21/74

Abstract:

An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

US Patent:

20220268805, Aug 25, 2022

Filed:

Feb 24, 2021

Appl. No.:

17/183432

Inventors:

- Malta NY, US
David C. Pritchard - Glenville NY, US
Elizabeth Strehlow - Malta NY, US
James P. Mazza - Saratoga Springs NY, US

Assignee:

GLOBALFOUNDRIES U.S. Inc. - Malta NY

International Classification:

G01P 15/00

Abstract:

Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

US Patent:

20210404867, Dec 30, 2021

Filed:

Jun 25, 2020

Appl. No.:

16/911950

Inventors:

- Malta NY, US
Ajey Poovannummoottil Jacob - Watervliet NY, US
Yusheng Bian - Ballston Lake NY, US
David C. Pritchard - Glenville NY, US

Assignee:

GLOBALFOUNDRIES U.S. Inc. - Malta NY

International Classification:

G01J 1/44
H01L 27/22
H01L 43/04
H01L 43/06
H04N 5/374
H04N 5/359

Abstract:

An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.