David Joseph Pruitt

US Patent:

6458076, Oct 1, 2002

Filed:

Feb 1, 2000

Appl. No.:

09/495810

Inventors:

David L. Pruitt - Union City CA

Assignee:

5 Star Medical - San Jose CA

International Classification:

A61B 100

US Classification:

600146, 600139, 600128

Abstract:

A multi-lumen medical device such as an endoscope or a catheter includes a shaft and a distal tip which are formed as multi-lumen extrusions having a large central working channel and a plurality of surrounding auxiliary lumens. The auxiliary lumens are arranged around the central working channel in a uniform manner so that the flexibility of the extruded member is uniform in a plurality of different directions. Use of the multi-lumen extrusion for the medical device provides a balanced device with a flexibility which is substantially the same in all directions. The medical device may be provided with four way tip deflection by providing four pull wires within four of the auxiliary lumens.

US Patent:

6703692, Mar 9, 2004

Filed:

Jan 31, 2002

Appl. No.:

10/066030

Inventors:

David A. Pruitt - San Jose CA

Assignee:

Linear Technology Corp. - Milpitas CA

International Classification:

H01L 23495

US Classification:

257666, 257667, 257670, 257676, 257787

Abstract:

A leadframe is disclosed. The leadframe comprises a frame characterized by a substantially rectangular outline, a die paddle with a receiving surface, and a plurality of support members that connect the frame to the die paddle. The leadframe further comprises a plurality of leads connected to the frame, that will eventually serve to electrically connect an integrated circuit mounted on the die paddle to an external electrical device. The die paddle lies in a lower horizontal plane. A plurality of support members connect the frame with the die paddle. As projected on to a vertical plane that is perpendicular to the side of the frame to which a support member is attached, the offset angle between the support member and a vertical axis is less than 45 degrees.

US Patent:

7154165, Dec 26, 2006

Filed:

Jul 21, 2004

Appl. No.:

10/895095

Inventors:

David Pruitt - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 23/495
H01L 23/48
H01L 23/52

US Classification:

257670, 257666, 257669

Abstract:

A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.

US Patent:

7414302, Aug 19, 2008

Filed:

Aug 8, 2006

Appl. No.:

11/500359

Inventors:

David Pruitt - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 23/495
H01L 23/48

US Classification:

257669, 257670, 257666, 257E23037

Abstract:

A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.

US Patent:

7902665, Mar 8, 2011

Filed:

Sep 2, 2008

Appl. No.:

12/202835

Inventors:

David Alan Pruitt - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 23/34

US Classification:

257725, 257666, 257686, 257777, 257E23031, 257E23085

Abstract:

A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

US Patent:

7960845, Jun 14, 2011

Filed:

Jan 3, 2008

Appl. No.:

12/003883

Inventors:

David Alan Pruitt - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 21/60
H01L 23/495
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257784, 257401, 257691, 257779, 257735, 257672

Abstract:

A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

US Patent:

8076181, Dec 13, 2011

Filed:

Oct 22, 2010

Appl. No.:

12/910676

Inventors:

David A. Pruitt - San Jose CA, US
Lothar Maier - Pleasanton CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44
H01L 21/46

US Classification:

438111, 438106, 438123, 438124, 438127, 438458, 257E21499, 257E21502, 257E21503, 257E21506, 257E21511

Abstract:

A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.

US Patent:

8163643, Apr 24, 2012

Filed:

May 4, 2010

Appl. No.:

12/773477

Inventors:

Maurice O. Othieno - Alameda CA, US
Ramaswamy Ranganathan - Saratoga CA, US
Frederick E. Beville - San Jose CA, US
David A. Pruitt - San Jose CA, US
William D. Griffitts - Santa Clara CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H01L 21/44

US Classification:

438612, 438106, 257678, 257E21499, 257E21506, 257E21509

Abstract:

A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.