David J Rae

US Patent:

20210351145, Nov 11, 2021

Filed:

May 6, 2020

Appl. No.:

16/868349

Inventors:

- San Diego CA, US
David Fraser RAE - San Diego CA, US
Hong Bok WE - San Diego CA, US

International Classification:

H01L 23/00
H01L 23/31
H01L 21/56

Abstract:

A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.

US Patent:

20210280523, Sep 9, 2021

Filed:

Jun 30, 2020

Appl. No.:

16/916339

Inventors:

- San Diego CA, US
Aniket Patil - San Diego CA, US
Marcus Hsu - San Diego CA, US
David Fraser Rae - San Diego CA, US

International Classification:

H01L 23/538
H01L 23/31
H01L 23/00
H01L 21/48
H01L 21/56

Abstract:

Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other exemplary aspects, the top and bottom metallization structures can include redistribution layers (RDLs) to provide increased electrical conductivity between die interconnects and substrate interconnects.

US Patent:

20210104507, Apr 8, 2021

Filed:

Oct 2, 2019

Appl. No.:

16/591374

Inventors:

- San Diego CA, US
Hong Bok WE - San Diego CA, US
David Fraser RAE - San Diego CA, US

International Classification:

H01L 25/00
H01L 23/00
H01L 23/498

Abstract:

Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.

US Patent:

20190341352, Nov 7, 2019

Filed:

May 2, 2018

Appl. No.:

15/968774

Inventors:

- San Diego CA, US
Jaehyun YEON - San Diego CA, US
Manuel ALDRETE - Encinitas CA, US
David Fraser RAE - San Diego CA, US

International Classification:

H01L 23/552
H01L 23/31
H01L 23/498
H01L 21/48
H01L 21/56
H01L 21/78
H01L 21/683
H01L 21/3105
H01L 23/29

Abstract:

A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.

US Patent:

20170271289, Sep 21, 2017

Filed:

Mar 16, 2016

Appl. No.:

15/072315

Inventors:

- San Diego CA, US
David Fraser RAE - San Diego CA, US
Reynante Tamunan ALVARADO - San Diego CA, US

International Classification:

H01L 23/00
H01L 23/29
H01L 21/56
H01L 23/31

Abstract:

A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.

US Patent:

20160372446, Dec 22, 2016

Filed:

Jul 28, 2015

Appl. No.:

14/811261

Inventors:

- San Diego CA, US
David Fraser Rae - San Diego CA, US
Piyush Gupta - San Diego CA, US

International Classification:

H01L 25/065
H01L 25/00
H01L 25/18
H01L 23/31
H01L 21/311
H01L 21/768
H01L 23/522
H01L 23/528
H01L 23/00
H01L 21/56

Abstract:

An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (μm) or less.

US Patent:

20160315072, Oct 27, 2016

Filed:

Aug 27, 2015

Appl. No.:

14/837917

Inventors:

- San Diego CA, US
David Fraser Rae - San Diego CA, US

International Classification:

H01L 25/10

Abstract:

Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.

US Patent:

20160218064, Jul 28, 2016

Filed:

Jan 22, 2015

Appl. No.:

14/603166

Inventors:

- San Diego CA, US
David Fraser RAE - San Diego CA, US
Rajneesh KUMAR - San Diego CA, US
Milind Pravin SHAH - San Diego CA, US
Omar James BCHIR - San Marcos CA, US

International Classification:

H01L 23/538
H01L 25/16
H01L 25/065
H01L 25/18
H01L 25/00
H01L 23/00

Abstract:

A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.