David R Rasmussen

US Patent:

6449732, Sep 10, 2002

Filed:

Dec 18, 1999

Appl. No.:

09/467669

Inventors:

David C. Rasmussen - Placentia CA
John G. Gabler - Irvine CA
Ronald L. Popp - Lake Forest CA

Assignee:

Triconex Corporation - Irvine CA

International Classification:

G06F 1118

US Classification:

714 12, 713400

Abstract:

A controller for executing an application program to process control information related to control elements includes one or more main processors that each run the application program; a time synchronization system that synchronizes the time clocks of the main processors; and a voting system that exchanges information between the main processors and compares the information received from the other main processors. In addition, the controller includes one or more rendezvous signals sent to and received by the main processors as well as a mechanism for updating the time clocks based on a clocking midpoint of all processor signals.

US Patent:

6754846, Jun 22, 2004

Filed:

Aug 22, 2002

Appl. No.:

10/226454

Inventors:

David C. Rasmussen - Placentia CA
John C. Gabler - Irvine CA
Ronald L. Popp - Lake Forest CA

Assignee:

Invensys Systems, Inc. - Foxboro MA

International Classification:

G06F 1100

US Classification:

714 11, 714 12, 714797

Abstract:

A control system for executing an application program is disclosed herein. The control system includes a plurality of main processor modules. The control system further includes a plurality of input/output modules for providing input process data to associated ones of the plurality of main processor modules. A voting system is operative to compare the input process data associated with first and second of the plurality of main processor modules to the input process data associated with a third of the main processor modules. This results in generation of voted input process data utilized by the third main processor module in executing the application program. In certain implementations the system includes a high-speed bus for distributing the voted input process data to the first and second main processor modules, each of which also executes the application program based upon the voted input process data.

US Patent:

6988221, Jan 17, 2006

Filed:

May 17, 2004

Appl. No.:

10/848542

Inventors:

David C. Rasmussen - Placentia CA, US
John G. Gabler - Irvine CA, US
Ronald L. Popp - Lake Forest CA, US

Assignee:

Triconex - Irvine CA

International Classification:

G06F 11/00

US Classification:

714 12, 713375

Abstract:

A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.

US Patent:

8037356, Oct 11, 2011

Filed:

Oct 24, 2007

Appl. No.:

11/923534

Inventors:

David C. Rasmussen - Placentia CA, US
John G. Gabler - Irvine CA, US

International Classification:

G06F 11/00

US Classification:

714 31, 714716, 370249

Abstract:

A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

US Patent:

20060031713, Feb 9, 2006

Filed:

Oct 3, 2005

Appl. No.:

11/242401

Inventors:

David Rasmussen - Placentia CA, US
John Gabler - Irvine CA, US

International Classification:

G06F 11/00

US Classification:

714012000

Abstract:

A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.