David H Ray

US Patent:

6446167, Sep 3, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435861

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

711122, 711 3, 711118, 711119, 711133, 711137, 711144

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

US Patent:

6460115, Oct 1, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435865

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

711122, 711137, 711213, 712207

Abstract:

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

US Patent:

6463514, Oct 8, 2002

Filed:

Feb 18, 1998

Appl. No.:

09/025605

Inventors:

David Scott Ray - Georgetown TX
Shih-Hsiung Stephen Tung - Austin TX
Pei Chun Liu - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711168, 711210, 711220

Abstract:

A method of arbitrating between cache access circuits (i. e. , load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

US Patent:

6535962, Mar 18, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/435860

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711137, 711122, 711204, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

US Patent:

6574712, Jun 3, 2003

Filed:

Apr 14, 2000

Appl. No.:

09/550180

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel M. Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711137, 711122, 711213, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

US Patent:

6915415, Jul 5, 2005

Filed:

Jan 7, 2002

Appl. No.:

10/042102

Inventors:

Michael John Mayfield - Austin TX, US
Francis Patrick O'Connell - Austin TX, US
David Scott Ray - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/30

US Classification:

712225, 712205, 711137

Abstract:

A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

US Patent:

6957305, Oct 18, 2005

Filed:

Aug 29, 2002

Appl. No.:

10/232248

Inventors:

David Scott Ray - Georgetown TX, US
David J. Shippy - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711137, 711118, 711125, 711138, 711204, 712205, 712206, 712207

Abstract:

This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a Lcache. A second synchronous form of a DCBT instruction is used to prefetch data from the Lcache to the CRB in the main CPU, which will bypass the Ldata cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

US Patent:

7302527, Nov 27, 2007

Filed:

Nov 12, 2004

Appl. No.:

10/988284

Inventors:

Brian David Barrick - Pflugerville TX, US
Kimberly Marie Fernsler - Round Rock TX, US
Dwain A. Hicks - Pflugerville TX, US
Takeki Osanai - Austin TX, US
David Scott Ray - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711125, 711137, 711140, 711204, 712216

Abstract:

Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to generate an address of the needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load and/or store instruction specifying the same address. If such a previous load/store instruction is found, the thread information is used to determine if the previous load/store instruction is from the same thread. If the previous load/store instruction is from the same thread, the cache hit signal is ignored, and the load instruction is stored in the queue. A load/store unit is also described.