David Allen Russo

US Patent:

6546477, Apr 8, 2003

Filed:

Sep 20, 2000

Appl. No.:

09/666044

Inventors:

David A. Russo - Santa Barbara CA
Robert E. Frankel - Goleta CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1202

US Classification:

711170, 717100

Abstract:

A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. A plurality of algorithm modules is combined with a framework to form the software program. Each of the plurality of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The software program is then loaded on a hardware platform and executed. During execution, the framework sends a query to the memory interface of each of the plurality of algorithm modules to request memory usage requirements for each instance of each of the plurality of algorithm modules. A response is then sent from the memory interface of each algorithm module identifying memory usage requirements for each instance of the algorithm module. The framework then allocates a portion of memory to each algorithm module to instantiate each instance in accordance with the memory usage requirement identified by the memory interface of each algorithm module.

US Patent:

6560722, May 6, 2003

Filed:

Dec 30, 1999

Appl. No.:

09/475818

Inventors:

Robert Frankel - Goleta CA
Elizabeth G. Keate - Santa Barbara CA
Gilbert A. Pitney - Santa Barbara CA
David A. Russo - Santa Barbara CA
Karl Wechsler - Santa Barbara CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 174

US Classification:

714 38, 717125, 717128

Abstract:

To address the need for enhanced real-time analysis, Texas Instruments Inc. has developed a standard embedded infrastructure for its DSPs that provides unique visibility into real-time program execution. Integrated with TIs Code Composer Studio development environment, this infrastructure consists of two components: 1) DSP/BIOS, a tiny target-based run-time system that captures event and statistical information for the application and uploads it to the host (via a standard physical link such as JTAG) as the application executes in real-time; this DSP/BIOS system is integrated with the target application (C or DSP assembler); 2) Scope, a suite of host-based tools that allows designers to visually trace, monitor, and probe the DSP application as it executes in real time. Even after the Code composer debugger halts the program and assumes control of the target, information already captured through embedded DSP/BIOS instrumentation can provide valuable insight into the sequence of events that led up to the current point of execution.

US Patent:

6691298, Feb 10, 2004

Filed:

Sep 20, 2000

Appl. No.:

09/667393

Inventors:

David A. Russo - Santa Barbara CA
Robert E. Frankel - Goleta CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 944

US Classification:

717100, 717108, 711170

Abstract:

A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. During a design phase of an application, a set of algorithm modules is linked with a calling program to form an initial software program. Each of the set of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The calling program sends a query to the memory interface of each algorithm module to request memory usage requirements for each instance of the algorithm module. A response is then sent from the memory interface of each algorithm module identifying memory usage requirements for each instance of the algorithm module. The calling program then allocates a portion of memory to each algorithm module to instantiate each instance in accordance with the memory usage requirement identified by the memory interface of each algorithm module.

US Patent:

6820184, Nov 16, 2004

Filed:

Jan 31, 2003

Appl. No.:

10/355924

Inventors:

David A. Russo - Santa Barbara CA
Robert E. Frankel - Goleta CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1202

US Classification:

711170, 717100

Abstract:

A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. A plurality of algorithm modules is combined with a framework to form the software program. Each of the plurality of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The software program is then loaded on a hardware platform and executed. During execution, the framework sends a query to the memory interface of each of the plurality of algorithm modules to request memory usage requirements for each instance of each of the plurality of algorithm modules. A response is then sent from the memory interface of each algorithm module identifying memory usage requirements for each instance of the algorithm module. The framework then allocates a portion of memory to each algorithm module to instantiate each instance in accordance with the memory usage requirement identified by the memory interface of each algorithm module.

US Patent:

6968438, Nov 22, 2005

Filed:

Sep 20, 2000

Appl. No.:

09/666629

Inventors:

David A. Russo - Santa Barbara CA, US
Robert E. Frankel - Goleta CA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F012/02

US Classification:

711170, 717100

Abstract:

A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. An algorithm module is designed in a manner that renders the algorithm module reentrant within a preemptive environment. Each data access instruction of the algorithm module is coded in a manner that renders the algorithm module and all of the data access instructions relocatable. A memory interface is provided within the algorithm module that supports both design-time object instantiation and dynamic object instantiation.

US Patent:

52839001, Feb 1, 1994

Filed:

Oct 2, 1989

Appl. No.:

7/415882

Inventors:

Robert E. Frankel - Santa Barbara CA
David M. Lindsay - Santa Barbara CA
David A. Russo - Santa Barbara CA
David Y. Wong - Santa Barbara CA

Assignee:

Spectron Microsystems, Inc. - Santa Barbara CA

International Classification:

G06F 9455
G06F 1531
G06F 15332
G06F 15347

US Classification:

395700

Abstract:

A data processor, such as a digital signal processor, that has augmented memory, I/O and math units for real-time performance of complex functions, is placed under the control of a group of abstract object-oriented modules arranged with an underlying operational nucleus that includes a real-time kernel. The modules are hierarchically configured, with the lowest being an array object type that references memory allocations. A stream object type, based on the arrays, defines channels between application software and data devices. A vector object type, also based on the arrays, establishes structure within allocated blocks and also enables vector math functions to be undertaken by the vector module. Matrix and filter object types utilize the arrays and vectors in sequences controlled by the corresponding matrix and vector modules. The system provides a model of DSP functionality that is hardware independent, and an interface between high level language calls and highly efficient routines executed in assembly language.

US Patent:

53924487, Feb 21, 1995

Filed:

Dec 14, 1993

Appl. No.:

8/166553

Inventors:

Robert E. Frankel - Santa Barbara CA
David M. Lindsay - Santa Barbara CA
David A. Russo - Santa Barbara CA
David Y. Wong - Santa Barbara CA

Assignee:

Spectron MicroSystems, Inc. - Goleta CA

International Classification:

G06F 1520

US Classification:

395800

Abstract:

A data processor, such as a digital signal processor, that has augmented memory, I/O and math units for real-time performance of complex functions, is placed under the control of a group of abstract object-oriented modules arranged with an underlying operational nucleus that includes a real-time kernel. The modules are hierarchically configured, with the lowest being an array object type that references memory allocations. A stream object type, based on the arrays, defines channels between application software and data devices. A vector object type, also based on the arrays, establishes structure within allocated blocks and also enables vector math functions to be undertaken by the vector module. Matrix and filter object types utilize the arrays and vectors in sequences controlled by the corresponding matrix and vector modules. The system provides a model of DSP functionality that is hardware independent, and an interface between high level language calls and highly efficient routines executed in assembly language.