David W Scheid

US Patent:

7979746, Jul 12, 2011

Filed:

Apr 27, 2009

Appl. No.:

12/430658

Inventors:

Brian Cornelius - Glendale AZ, US
Mitch Fletcher - Glendale AZ, US
James Alexander Ross - Phoenix AZ, US
David Scheid - Eau Claire WI, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 37, 714 30

Abstract:

Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.