David Alan Schultz

US Patent:

6353334, Mar 5, 2002

Filed:

Jan 27, 2000

Appl. No.:

09/492560

Inventors:

David P. Schultz - San Jose CA
Brian Von Herzen - Carson City NV
Jon A. Brunetti - Stateline NV

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 190185

US Classification:

326 82, 326 86, 326 30, 326 90

Abstract:

Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.

US Patent:

6366128, Apr 2, 2002

Filed:

Sep 5, 2000

Appl. No.:

09/655168

Inventors:

Atul V. Ghia - San Jose CA
Suresh M. Menon - Sunnyvale CA
David P. Schultz - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19094

US Classification:

326 83, 326 44, 326 40, 326 49

Abstract:

Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

US Patent:

6429682, Aug 6, 2002

Filed:

May 25, 2001

Appl. No.:

09/865813

Inventors:

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19173

US Classification:

326 41, 326 38, 326 39

Abstract:

A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

US Patent:

6445245, Sep 3, 2002

Filed:

Oct 6, 2000

Appl. No.:

09/684539

Inventors:

David P. Schultz - San Jose CA
Suresh M. Menon - Sunnyvale CA
Eunice Y. D. Hao - Saratoga CA
Jason R. Bergendahl - Campbell CA
Jian Tan - Milpitas CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G05F 110

US Classification:

327541, 327543

Abstract:

A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

US Patent:

6489837, Dec 3, 2002

Filed:

Nov 30, 2001

Appl. No.:

10/007167

Inventors:

David P. Schultz - San Jose CA
Suresh M. Menon - Sunnyvale CA
Eunice Y. D. Hao - Saratoga CA
Jason R. Bergendahl - Campbell CA
Jian Tan - Milpitas CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G05F 110

US Classification:

327541, 327566, 36523003

Abstract:

A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

US Patent:

6507211, Jan 14, 2003

Filed:

Jul 29, 1999

Appl. No.:

09/363990

Inventors:

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 738

US Classification:

326 37, 326 38, 326 39

Abstract:

A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

US Patent:

6525562, Feb 25, 2003

Filed:

Apr 30, 2002

Appl. No.:

10/136141

Inventors:

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39, 326 41

Abstract:

A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The state data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

US Patent:

6526466, Feb 25, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/438220

Inventors:

Scott O. Frake - Cupertino CA
James L. McManus - Campbell CA
David P. Schultz - San Jose CA
Wilson K. Yee - Pleasanton CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

710302, 327530

Abstract:

An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.