David A Seberger

US Patent:

61956767, Feb 27, 2001

Filed:

Jan 11, 1993

Appl. No.:

8/003000

Inventors:

George A. Spix - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Stuart W. Hawkinson - Eau Claire WI
Mark D. Johnson - Eau Claire WI
Jeremiah D. Burke - Eau Claire WI
Keith J. Thompson - Eau Claire WI
Gregory G. Gaertner - Eau Claire WI
Giacomo G. Brussino - Eau Claire WI
Richard E. Hessel - Altoona WI
David M. Barkai - Eau Claire WI
Steve S. Chen - Chippewa Falls WI
Steven G. Oslon - Chippewa Falls WI
Robert E. Strout - Livermore CA
Jon A. Masamitsu - Livermore CA
David M. Cox - Livermore CA
Linda J. O'Gara - Livermore CA
Kelly T. O'Hair - Livermore CA
David A. Seberger - Livermore CA
James C. Rasbold - Livermore CA
Timothy J. Cramer - Pleasanton CA
Don A. Van Dyke - Pleasanton CA
Ashok Chandramouli - Fremont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 946

US Classification:

709107

Abstract:

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

US Patent:

51758563, Dec 29, 1992

Filed:

Aug 23, 1990

Appl. No.:

7/572043

Inventors:

Don A. Van Dyke - Pleasanton CA
Timothy J. Cramer - Pleasanton CA
James C. Rasbold - Livermore CA
Kelly T. O'Hair - Livermore CA
David M. Cox - Livermore CA
David A. Seberger - Livermore CA
Linda J. O'Gara - Livermore CA
Jon A. Masamitsu - Livermore CA
Robert E. Strout - Livermore CA
Ashok Chandramouli - Fremont CA

Assignee:

Supercomputer Systems Limited Partnership - Eau Claire WI

International Classification:

G06F 1516

US Classification:

395700

Abstract:

A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.

US Patent:

51931923, Mar 9, 1993

Filed:

Aug 23, 1990

Appl. No.:

7/571502

Inventors:

David A. Seberger - Livermore CA

Assignee:

Supercomputer Systems Limited Partnership - Eau Claire WI

International Classification:

G06F 945

US Classification:

395700

Abstract:

A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one relationship exists between each lookahead set in the lookahead set table and the representation of the lookahead set in the lookahead set table. In a read transition portion of the parser, an entrance symbol table has entries paired with transition state representations and each pair being at an identical address offset in the respective tables. For a reduction or read transition operation, the lookahead set table or the entrance symbol table is scanned to find the appropriate entry. Once the appropriate entry is found, the production table or the transition state table is addressed using the offset of the appropriate entry found during the scanning process.

US Patent:

51797020, Jan 12, 1993

Filed:

Jun 11, 1990

Appl. No.:

7/537466

Inventors:

George A. Spix - Eau Claire WI
Diane M. Wengelski - Eau Claire WI
Stuart W. Hawkinson - Eau Claire WI
Mark D. Johnson - Eau Claire WI
Jeremiah D. Burke - Eau Claire WI
Keith J. Thompson - Eau Claire WI
Gregory G. Gaertner - Eau Claire WI
Giacomo G. Brussino - Eau Claire WI
Richard E. Hessel - Altoona WI
David M. Barkai - Eau Claire WI
Steve S. Chen - Chippewa Falls WI
Steven G. Oslon - Chippewa Falls WI
Robert E. Strout - Livermore CA
Jon A. Masamitsu - Livermore CA
David M. Cox - Livermore CA
Linda J. O'Gara - Livermore CA
Kelly T. O'Hair - Livermore CA
David A. Seberger - Livermore CA
James C. Rasbold - Livermore CA
Timothy J. Cramer - Pleasanton CA
Don A. Van Dyke - Pleasanton CA
Ashok Chandramouli - Fremont CA

Assignee:

Supercomputer Systems Limited Partnership - Eau Claire WI

International Classification:

G06F 946

US Classification:

395650

Abstract:

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

US Patent:

60187999, Jan 25, 2000

Filed:

Jul 22, 1998

Appl. No.:

9/121167

Inventors:

David R. Wallace - San Francisco CA
David M. Cox - Livermore CA
Serguei V. Morosov - Novosibirsk, RU
David A. Seberger - Livermore CA
Serguei L. Wenitsky - Novosibirsk, RU

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 934
G06F 1204

US Classification:

712300

Abstract:

Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.