David R Shumate

US Patent:

20090014791, Jan 15, 2009

Filed:

Jul 8, 2008

Appl. No.:

12/169349

Inventors:

Samuel J. Anderson - Tempe AZ, US
David N. Okada - Chandler AZ, US
Gary Dashney - Phoenix AZ, US
David A. Shumate - Phoenix AZ, US

Assignee:

GREAT WALL SEMICONDUCTOR CORPORATION - Tempe AZ

International Classification:

H01L 27/06
H01L 21/8234

US Classification:

257337, 438237, 257E27016, 257E21616

Abstract:

A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.

US Patent:

20090321784, Dec 31, 2009

Filed:

Jun 23, 2009

Appl. No.:

12/490112

Inventors:

Samuel J. Anderson - Tempe AZ, US
David N. Okada - Chandler AZ, US
David A. Shumate - Phoenix AZ, US
Gary Dashney - Phoenix AZ, US

Assignee:

GREAT WALL SEMICONDUCTOR CORPORATION - Tempe AZ

International Classification:

H01L 25/07
H01L 21/328

US Classification:

257140, 438135, 438237, 257341, 257E25014, 257E2135

Abstract:

A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit.

US Patent:

20110140200, Jun 16, 2011

Filed:

Dec 24, 2010

Appl. No.:

12/978476

Inventors:

Samuel J. Anderson - Tempe AZ, US
David N. Okada - Chandler AZ, US
Gary Dashney - Phoenix AZ, US
David A. Shumate - Phoenix AZ, US

Assignee:

GREAT WALL SEMICONDUCTOR CORPORATION - Tempe AZ

International Classification:

H01L 27/06

US Classification:

257337, 257E27016

Abstract:

A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.

US Patent:

51734494, Dec 22, 1992

Filed:

Jan 7, 1991

Appl. No.:

7/634969

Inventors:

Kevin A. Lorenzen - Phoenix AZ
Dan L. Burt - Phoenix AZ
David A. Shumate - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2100
H01L 2102
H01L 2128
H01L 2148

US Classification:

437192

Abstract:

An improved process is described for depositing TiW/TiWN/TiW/Au metallization which provides superior adhesion properties, excellent barrier properties and which is suitable for use with metal line widths of the order of one micron or smaller. It is important in order to obtain these properties to ensure that the layer immediately underlying the gold layer by substantially pure TiW deposited in a nitrogen free sputtering atmosphere. To this end, the gas supply manifolds and deposition chamber are purged and the chamber evacuated following deposition of the TiW layer and prior to deposition of the TiWN layer underlying the gold layer. A final TiW layer is also conveniently placed on top of the gold layer to act as an etching mask.

US Patent:

51376105, Aug 11, 1992

Filed:

Apr 15, 1991

Appl. No.:

7/684757

Inventors:

David A. Shumate - Phoenix AZ
Thomas R. Baker - Tempe AZ
Robert W. Gray - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

C23F 404

US Classification:

20419232

Abstract:

A sputter chamber with a rotatably mounted cathode nested in spacers, formed of the material sold under the trademark Teflon, and a quartz plate defining wafer receiving openings therethrough and affixed to the flat upper surface of the cathode in overlying relationship with the cathode and any exposed spacers to prevent sputtering of the spacers. If the material sold under the Trademark Teflon is sputtered fluorine containing ions are produced in the chamber plasma, which chemically etch masking materials such as titanium tungsten.

US Patent:

51148757, May 19, 1992

Filed:

May 24, 1991

Appl. No.:

7/705407

Inventors:

Thomas R. Baker - Tempe AZ
Bernard W. Boland - Phoenix AZ
David A. Shumate - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2176

US Classification:

437 62

Abstract:

A substantially planar dielectric wafer is formed by utilizing a polysilicon filler to remove surface irregularities (15, 15'). The polysilicon filler is formed by filling surface irregularities (15, 15') with polysilicon (19) and polishing the polysilicon (19) to form a substantially planar surface. A polishing stop (18) terminates the polishing and prevents damage to the wafer's isolated tubs (13). The polishing stop (18) can also be used as a mask during field oxide growth. The polysilicon filler also protects underlying areas (12) from subsequent etch operations. During subsequent field oxide growth, polysilicon layer (19) is converted to silicon dioxide which enhances dielectric isolation of each tub (13).