David Buxton Snyder

Address:

5549 N Northern Hl Dr, Tucson, AZ 85704

Phone:

5208878279

VIN:

KMHFC46F67A231621

Make:

HYUNDAI

Model:

AZERA

Year:

2007

US Patent:

20130082321, Apr 4, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/249594

Inventors:

Harmeet Sobti - Portland OR, US
Timothy K. McGuire - Beaverton OR, US
David L. Snyder - Beaverton OR, US
Scott J. Alberhasky - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257329, 438268, 257E29262, 257E2141

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.

US Patent:

20210242343, Aug 5, 2021

Filed:

Apr 22, 2021

Appl. No.:

17/302060

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 27/06
H01L 29/08

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

US Patent:

20200295185, Sep 17, 2020

Filed:

May 29, 2020

Appl. No.:

16/887776

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 27/06
H01L 29/08

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

US Patent:

20200091340, Mar 19, 2020

Filed:

Sep 13, 2018

Appl. No.:

16/130150

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 29/08
H01L 27/06

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.