David T Snyder

US Patent:

20130082321, Apr 4, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/249594

Inventors:

Harmeet Sobti - Portland OR, US
Timothy K. McGuire - Beaverton OR, US
David L. Snyder - Beaverton OR, US
Scott J. Alberhasky - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257329, 438268, 257E29262, 257E2141

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.

US Patent:

53115694, May 10, 1994

Filed:

Jun 5, 1992

Appl. No.:

7/893613

Inventors:

Joseph M. Brozovich - Woodridge IL
Nicholas M. DeVito - Naperville IL
Douglas C. Kroupa - Lisle IL
Paul E. Renn - Downers Grove IL
Paul M. Simek - Lisle IL
David A. Snyder - Naperville IL
James L. Turner - Lemont IL

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H04M 1104
H04M 1100
H04M 342

US Classification:

379 45

Abstract:

A line-based 911 system and method that completes an emergency call from a telephone to a PSAP comprising a multiplicity of operator stations connected by individual lines to a telephone switching system. An emergency call is routed to the termination ports of the switching system associated with a PSAP. Each of the termination ports is connected to one of the multiplicity of operator stations via its associated line, thereby establishing a path from the telephone to the operator station, the CPN of the calling telephone is delivered to the selected operator station and the operator station obtains location information of the telephone in accordance with the CPN, which is then displayed.

US Patent:

44699620, Sep 4, 1984

Filed:

Oct 26, 1981

Appl. No.:

6/315334

Inventors:

David E. Snyder - Santa Monica CA

Assignee:

Hughes Aircraft Company - El Segundo CA

International Classification:

H03K 19096
H03K 1920
H03K 17687
G11C 1928

US Classification:

307450

Abstract:

The present invention provides a circuit comprising (1) a logic element responsive to data of first and second negative voltage potentials, the logic element having a depletion mode MESFET data input gate, and (2) a depletion mode MESFET transmission gate operatively associated with the data input gate for enabling the selective serial transmission of data therethrough to the logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage of the data input gate being between approximately the first and second negative voltage potentials, the pinch-off threshold voltage of the transmission gate being between approximately the third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more negative than said third negative voltage potential.

US Patent:

20210242343, Aug 5, 2021

Filed:

Apr 22, 2021

Appl. No.:

17/302060

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 27/06
H01L 29/08

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

US Patent:

20200385845, Dec 10, 2020

Filed:

Nov 28, 2018

Appl. No.:

16/767537

Inventors:

- Evanston IL, US
Gregory B. Olson - Riverwoods IL, US
David R. Snyder - Warrenville IL, US

International Classification:

C22C 21/08
B22F 9/08
B22F 3/105
B22F 3/24
B33Y 40/10
B33Y 70/00

Abstract:

Materials, methods and techniques disclosed and contemplated herein relate to aluminum alloys. Generally, multicomponent aluminum alloys include aluminum, magnesium, silicon, and, in some instances, iron and/or manganese, and include Mg2Si phase precipitates. Example multicomponent aluminum alloys disclosed and contemplated herein are particularly suited for use in additive manufacturing operations.

US Patent:

20200370149, Nov 26, 2020

Filed:

Nov 28, 2018

Appl. No.:

16/767516

Inventors:

- Evanston IL, US
Gregory B. Olson - Riverwoods IL, US
David R. Snyder - Des Plaines IL, US

International Classification:

C22C 21/00
C22C 1/04
C21D 9/00
B22F 3/105

Abstract:

Materials, methods and techniques disclosed and contemplated herein relate to multicomponent aluminum alloys. Generally, multicomponent aluminum alloys include aluminum, nickel, zirconium, and rare earth elements, and include L precipitates having an AlX composition. Rare earth elements used in example multicomponent aluminum alloys disclosed and contemplated herein include erbium (Er), zirconium (Zr), yttrium (Y), and ytterbium (Yb). Example multicomponent aluminum alloys disclosed and contemplated herein are particularly suited for use in additive manufacturing operations.

US Patent:

20200295185, Sep 17, 2020

Filed:

May 29, 2020

Appl. No.:

16/887776

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 27/06
H01L 29/08

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

US Patent:

20200091340, Mar 19, 2020

Filed:

Sep 13, 2018

Appl. No.:

16/130150

Inventors:

- Singapore, SG
David Snyder - Beaverton OR, US

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/78
H01L 29/10
H01L 29/08
H01L 27/06

Abstract:

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm, a gate charge (Qg) of about 1.9-2.0 nC/mm, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.