David R Stauffer

US Patent:

6993671, Jan 31, 2006

Filed:

Mar 28, 2003

Appl. No.:

10/249291

Inventors:

Douglas C. Pricer - Somerset NJ, US
David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713400, 713401

Abstract:

A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.

US Patent:

7191383, Mar 13, 2007

Filed:

Mar 28, 2003

Appl. No.:

10/249290

Inventors:

Ming-I M. Lin - South Burlington VT, US
David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714774, 714758

Abstract:

A system for generating CRC code words associated with data ranging up to w-bytes in width. The system is an iterative approach for providing a CRC calculation circuitry with the CRC calculation being subdivided into a blocks with selectable bus widths which blocks can be cascaded to provide calculation for a parallel bus width of any arbitrary number of bytes. The circuitry includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input such that any number of data input bytes may be processed.

US Patent:

7242737, Jul 10, 2007

Filed:

Jul 9, 2003

Appl. No.:

10/604296

Inventors:

Sheehan D. Lake - Burlington VT, US
David R. Stauffer - Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 25/00

US Classification:

375372

Abstract:

A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a first clock domain and latching the received data in a second clock domain by one of a first edge of a second clock signal, or a second opposite edge of the second clock signal. The first and second clock signals are of the same frequency but operating out of phase. A control circuit receives the first and second clock signals and determines a phase relationship therebetween. The control circuit generates a control signal based on the determined phase relationship which is implemented for selecting one of a rising edge of the second clock signal, or a falling edge of the second clock signal, for latching action in the second clock domain. Reliable data transfer operation is provided for all possible phase relationships of the first and second clock signals.

US Patent:

7290238, Oct 30, 2007

Filed:

May 12, 2004

Appl. No.:

10/709528

Inventors:

David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

An automated bit-sliced datapath system generating tool is built so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

US Patent:

7370542, May 13, 2008

Filed:

Jul 10, 2006

Appl. No.:

11/483430

Inventors:

David B. Stauffer - New Holland PA, US
George Korlinchak - New Holland PA, US

Assignee:

CNH America LLC - New Holland PA

International Classification:

G01L 1/04

US Classification:

73862453, 73 7, 73 8, 731181, 73812

Abstract:

The apparatus is a multi-speed flat belt durability tester that can simultaneously test several belts of different lengths. The tester can apply different tensions to each belt with a tension pulley powered by a hydraulic cylinder, and it monitors the tracking of the belts with photocell sensors. At least two belt test positions located at the outer edges of the apparatus include cantilevered pulley ends that greatly facilitate installation and removal of the belts being tested.

US Patent:

7444258, Oct 28, 2008

Filed:

Dec 5, 2005

Appl. No.:

11/275035

Inventors:

Francis A. Kampf - Jeffersonville VT, US
David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/00
G06F 19/00

US Classification:

702119, 702123, 703 14, 370248

Abstract:

Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

US Patent:

8051359, Nov 1, 2011

Filed:

Feb 20, 2007

Appl. No.:

11/676653

Inventors:

Ming-I M. Lin - South Burlington VT, US
David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/09

US Classification:

714757, 714807

Abstract:

A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2+M to 2+M, where N is equal to log(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2−1+M to 2; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of data input bytes may be processed.

US Patent:

8135558, Mar 13, 2012

Filed:

Jul 9, 2008

Appl. No.:

12/169668

Inventors:

Francis A. Kampf - Jeffersonville VT, US
David R. Stauffer - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
G06F 19/00

US Classification:

702123, 738658, 738659, 324537, 32476201, 32476206, 375224, 702108, 702119, 702182, 702183, 702186, 703 21

Abstract:

Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.