David Tsang

US Patent:

20130154686, Jun 20, 2013

Filed:

Nov 29, 2012

Appl. No.:

13/689719

Inventors:

Agate Logic Inc. - Sunnyvale CA, US
David Tsang - Los Altos CA, US
Chao-Chiang Chen - Cupertino CA, US

Assignee:

Agate Logic Inc. - Sunnyvale CA

International Classification:

H03K 19/0175
H03K 3/02

US Classification:

326 40, 326 39, 327298

Abstract:

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

US Patent:

20180062654, Mar 1, 2018

Filed:

Feb 2, 2015

Appl. No.:

14/612076

Inventors:

Kai Keung Chan - Fremont CA, US
David Tsang - Los Altos CA, US
Chao-Chiang Chen - Cupertino CA, US

Assignee:

Agate Logic Inc. - Santa Clara CA

International Classification:

H03K 19/0175
H03K 19/02
H03K 19/177

Abstract:

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

US Patent:

20160210334, Jul 21, 2016

Filed:

Jan 15, 2015

Appl. No.:

14/598157

Inventors:

- San Francisco CA, US
Vijayasarathy Chakravarthy - Mountain View CA, US
David Tsang - San Francisco CA, US

Assignee:

SALESFORCE.COM, INC. - San Francisco CA

International Classification:

G06F 17/30
G06F 17/22
G06F 3/0484

Abstract:

The technology disclosed relates to a platform for ultra-fast, ad-hoc data exploration and faceted navigation on integrated, heterogeneous data sets. The disclosed apparatus and methods for deep linking and state preservation via a URL make it possible to share live data as rendered on a live dashboard, without saving a new state on a server every time data and dashboard elements are updated.