David G Turley

US Patent:

20190278932, Sep 12, 2019

Filed:

May 29, 2019

Appl. No.:

16/424558

Inventors:

- Santa Clara CA, US
DAVID P. TURLEY - North Plains OR, US
SERGIU D. GHETIE - Hillsboro OR, US
ZHANGPING CHEN - Hillsboro OR, US
JASON G. SANDRI - Gilbert AZ, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G06F 21/62
G11C 7/24
G11C 17/18
G11C 7/10
G06F 21/60

Abstract:

Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

US Patent:

20180095897, Apr 5, 2018

Filed:

Sep 30, 2016

Appl. No.:

15/283087

Inventors:

- Santa Clara CA, US
DAVID P. TURLEY - NORTH PLAINS OR, US
SERGIU D. GHETIE - HILLSBORO OR, US
ZHANGPING CHEN - HILLSBORO OR, US
JASON G. SANDRI - GILBERT AZ, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G06F 12/14
G06F 21/62

Abstract:

Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

US Patent:

20180096151, Apr 5, 2018

Filed:

Oct 1, 2016

Appl. No.:

15/283381

Inventors:

SERGIU D GHETIE - Hillsboro OR, US
NEERAJ S. UPASANI - Portland OR, US
SAGAR V. DALVI - Hillsoro OR, US
DAVID P. TURLEY - North Plains OR, US
JEANNE GUILLORY - Hillsboro OR, US
MARK D. CHUBB - Tacoma WA, US
ALLEN R. WISHMAN - Cornelius OR, US
SHAHROKH SHAHIDZADEH - Portland OR, US

International Classification:

G06F 21/57
G06F 21/72
G06F 9/44
G06K 7/10

Abstract:

Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.