David C Williamson

US Patent:

7003699, Feb 21, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/206829

Inventors:

Andrew B Swaine - Welwyn Garden City, GB
David J Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 11/00

US Classification:

714 30

Abstract:

The present invention provides a data processing apparatus and method for generating trace signals. The data processing apparatus comprises a component whose behaviour is to be traced, and a trace generation unit for receiving input signals from the component indicative of the behaviour, and for generating from the input signals high priority and low priority trace signals for outputting to a trace receiving device. The trace generation unit is responsive to assertion of a suppression signal from the trace receiving device to suppress generation of the low priority trace signals, with the aim of avoiding overflow of the trace receiving device. Furthermore, in the event that multiple trace modules are provided within a data processing apparatus, embodiments of the present invention provide funnel logic to enable the trace signals generated by those various trace modules to be combined into a single trace stream having a bandwidth which is less than the collective maximum bandwidth of the individual trace streams generated by the multiple trace modules.

US Patent:

7020768, Mar 28, 2006

Filed:

Feb 26, 2001

Appl. No.:

09/792643

Inventors:

Andrew Brookfield Swaine - Welwyn Garden, GB
Conrado Blasco Allué - Cherry Hinton, GB
Ian Victor Devereux - Fulbourn, GB
David James Williamson - Austin TX, US
Anthony Neil Berent - Stapleford, GB

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/44
G06F 11/36

US Classification:

712228, 712227

Abstract:

The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.

US Patent:

7080289, Jul 18, 2006

Filed:

Oct 10, 2001

Appl. No.:

09/973189

Inventors:

Andrew Brookfield Swaine - Welwyn Garden City, GB
David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 11/00

US Classification:

714 45, 714 30, 712227, 717128

Abstract:

A microprocessor integrated circuit is provided with a trace controller that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller is able to trigger tracing partway through that instruction such that a subset of the transfer specified by that instruction are included within the trace data stream. All transfers subsequent to the triggering transfer may be traced with those transfers subsequent to the triggering transfer being marked with place holder codes rather than more informative full trace data for the triggering transfer.

US Patent:

7093236, Aug 15, 2006

Filed:

Feb 1, 2001

Appl. No.:

09/773387

Inventors:

Andrew Brookfield Swaine - Welwyn Garden City, GB
David James Williamson - Austin TX, US
Paul Robert Gotch - Cambridge, GB

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/44
G06F 11/00

US Classification:

717128, 714 45

Abstract:

An integrated circuit is provided with a tracing mechanism that is responsive to data access misses to insert a data place holder within a stream of trace data. When the missed data is later returned, this is inserted into the stream of traced data as a later data value. Analysis of the stream trace data may subsequently correlate between instructions that gave rise to data misses and the late data that was subsequently returned.

US Patent:

7197671, Mar 27, 2007

Filed:

Jun 3, 2003

Appl. No.:

10/452904

Inventors:

Andrew B Swaine - Welwyn Garden City, GB
David J Williamson - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 11/00

US Classification:

714 45, 714 30, 717128, 717129, 712227

Abstract:

A trace module traces changes in a subset of architectural state of a data processing apparatus. A trace generation unit receives input signals from components of the data processing apparatus indicative of a change in the subset of architectural state and generates a number of trace elements indicative of the change to enable a recipient of the trace elements to subsequently reconstruct the subset of architectural state. A table maintained by the trace generation unit identifies an architectural state derivable from previously generated trace elements. The trace generation unit references the table to determine which trace elements to generate. The table reduces the number of trace elements that need to be generated by providing a record of the architectural state which has already been provided to the recipient. Only those trace elements relating to changes in architectural state which are not derivable by the recipient need be generated.

US Patent:

7343481, Mar 11, 2008

Filed:

Mar 19, 2003

Appl. No.:

10/391186

Inventors:

David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/38

US Classification:

712238, 712207, 712239, 711213

Abstract:

A data processing system incorporates an instruction prefetch unit including a static branch predictor. A static branch prediction cache is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode for that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor.

US Patent:

7389459, Jun 17, 2008

Filed:

Mar 22, 2005

Appl. No.:

11/085598

Inventors:

Conrado Blasco Allue - Austin TX, US
Stephen John Hill - Austin TX, US
David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G01R 31/28
G11C 29/00
G11C 7/00

US Classification:

714733, 714718, 365201

Abstract:

A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.

US Patent:

7437544, Oct 14, 2008

Filed:

Apr 29, 2005

Appl. No.:

11/117723

Inventors:

Ann Sekli Chin - Austin TX, US
David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 15/00

US Classification:

712241, 712215, 712 7

Abstract:

A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executing the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel. When executing instructions in parallel, the first processing path executes an instruction which is earlier in the sequence than the instruction executing in the second processing path. The processing unit is operable when executing a multiple iteration instruction to allow a first iteration of the multiple iteration instruction to be executed in either the first processing path or the second processing path, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path. This provides a particularly efficient technique for executing the sequence of instructions.