David R Winston

US Patent:

20190057757, Feb 21, 2019

Filed:

Oct 19, 2018

Appl. No.:

16/165549

Inventors:

- San Diego CA, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Jihoon Jeong - Cary NC, US
Hoan Huu Nguyen - Cary NC, US

International Classification:

G11C 29/52
G11C 11/418
G11C 11/412
H01L 27/11
G11C 11/00
G11C 11/419

Abstract:

Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

US Patent:

20180033465, Feb 1, 2018

Filed:

Sep 27, 2017

Appl. No.:

15/717028

Inventors:

- San Diego CA, US
Francois Ibrahim Atallah - Raleigh NC, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Hoan Huu Nguyen - Cary NC, US

International Classification:

G11C 5/14
G11C 11/419
G11C 7/12
G11C 11/413
G11C 8/08
G11C 15/04

Abstract:

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

US Patent:

20170316838, Nov 2, 2017

Filed:

Jul 10, 2017

Appl. No.:

15/645355

Inventors:

- San Diego CA, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Jihoon Jeong - Cary NC, US
Hoan Huu Nguyen - Durham NC, US

International Classification:

G11C 29/52
G11C 11/418
G11C 11/412
G11C 11/419
G11C 11/00

Abstract:

Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

US Patent:

20170090508, Mar 30, 2017

Filed:

Sep 25, 2015

Appl. No.:

14/865092

Inventors:

- San Diego CA, US
Anil KRISHNA - Raleigh NC, US
Raguram DAMODARAN - San Diego CA, US
Jeffrey Todd BRIDGES - Raleigh NC, US
Thomas Philip SPEIER - Wake Forest NC, US
Rodney Wayne SMITH - Raleigh NC, US
Keith Alan BOWMAN - Morrisville NC, US
David Joseph Winston HANSQUINE - Raleigh NC, US

International Classification:

G06F 1/08
G06F 12/12
G06F 12/08

Abstract:

The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

US Patent:

20160247555, Aug 25, 2016

Filed:

Sep 23, 2015

Appl. No.:

14/862483

Inventors:

- San Diego CA, US
Francois Ibrahim Atallah - Raleigh NC, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Jihoon Jeong - Cary NC, US

International Classification:

G11C 11/419

Abstract:

P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”) are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.

US Patent:

20160247556, Aug 25, 2016

Filed:

Sep 23, 2015

Appl. No.:

14/862555

Inventors:

- San Diego CA, US
Francois Ibrahim Atallah - Raleigh NC, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Hoan Huu Nguyen - Durham NC, US

International Classification:

G11C 11/419

Abstract:

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

US Patent:

20160247557, Aug 25, 2016

Filed:

Sep 23, 2015

Appl. No.:

14/862579

Inventors:

- San Diego CA, US
Francois Ibrahim Atallah - Raleigh NC, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Hoan Huu Nguyen - Durham NC, US

International Classification:

G11C 11/419

Abstract:

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

US Patent:

20160247558, Aug 25, 2016

Filed:

Sep 23, 2015

Appl. No.:

14/862636

Inventors:

- San Diego CA, US
Francois Ibrahim Atallah - Raleigh NC, US
Keith Alan Bowman - Morrisville NC, US
David Joseph Winston Hansquine - Raleigh NC, US
Hoan Huu Nguyen - Durham NC, US

International Classification:

G11C 11/419

Abstract:

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of a negative supply rail positive boost circuit can be employed to weaken an NFET pull-down transistor in a storage circuit of a memory bit cells having a PFET write port(s).