David Chengkai Yu

Address:

44007 Renoir Ter, Fremont, CA 94539

Phone:

5106571072

VIN:

2HNYD2H32CH504318

Make:

ACURA

Model:

MDX

Year:

2012

US Patent:

6526680, Mar 4, 2003

Filed:

Jan 23, 2002

Appl. No.:

10/052881

Inventors:

David Yu - New York NY

Assignee:

Electra Accessories Inc. - Cranbury NJ

International Classification:

G09F 1302

US Classification:

40204, 40209, 362497

Abstract:

A license plate holder for use on a vehicle has a frame that holds and displays a vehicle license plate on the vehicle. A plurality of red light emitting diodes (LEDs) is mounted around the perimeter of the frame. They are connected to the brake light circuit of the vehicle to light up when the brakes are applied. A lesser number of non-red LEDs are also disposed around the perimeter of the frame. These are connected to the running light circuit of the vehicle. They may be multi-colored or of a single color such as blue or green.

US Patent:

6806880, Oct 19, 2004

Filed:

Oct 17, 2000

Appl. No.:

09/688978

Inventors:

Shrijeet Mukherjee - Mountain View CA
David M. Blythe - San Carlos CA
David G. Yu - Menlo Park CA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06T 120

US Classification:

345506, 345545, 345539, 345522, 345556

Abstract:

A system and method for controlling graphics rendering pipelines. The pipeline is unstalled in response to a display interval complete signal which allows pipeline processing to proceed even at the beginning of a tolerance interval. A stall controller unstalls processing of the graphics data in the graphics rendering pipeline when a display interval complete signal has been generated. A stall token installer inserts stall tokens in between frames of the graphics data. A queue stores frame complete markers in an order matching the order of stall tokens inserted in between frames of graphics data.

US Patent:

7358974, Apr 15, 2008

Filed:

Jan 29, 2002

Appl. No.:

10/058050

Inventors:

David R. Blythe - San Carlos CA, US
Marc Schafer - Naples, IT
Paul Jeffrey Ungar - Mountain View CA, US
David Yu - San Francisco CA, US

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 15/80
G06T 15/30

US Classification:

345505, 345423, 345418

Abstract:

A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is direct function of the size of a given subarea and a function of the rendering complexity for objects within this subarea. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the subareas. The cost of this approach is the necessity to communicate, in conjunction with each frame, the graphics data that will be rendered. Graphics data for a frame is composed of geometry chunks.

US Patent:

7737982, Jun 15, 2010

Filed:

Apr 15, 2008

Appl. No.:

12/103586

Inventors:

David R. Blythe - San Carlos CA, US
Marc Schafer - Naples, IT
Paul Jeffrey Ungar - Mountain View CA, US
David Yu - San Francisco CA, US

Assignee:

Graphics Properties Holdings, Inc. - Palo Alto CA

International Classification:

G06F 15/80

US Classification:

345505, 345423, 345418

Abstract:

A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given subarea and a function of the rendering complexity for objects within this subarea. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the subareas. The cost of this approach is the necessity to communicate, in conjunction with each frame, the graphics data that will be rendered. Graphics data for a frame is composed of geometry chunks.

US Patent:

7764536, Jul 27, 2010

Filed:

Aug 7, 2007

Appl. No.:

11/834917

Inventors:

Xiao Luo - Cupertino CA, US
David Chang-Cheng Yu - Pleasanton CA, US

Assignee:

Grandis, Inc. - Milpitas CA
Renesas Technology Corp. - Tokyo

International Classification:

G11C 11/00

US Classification:

365158, 365157, 365148, 365171, 365173, 365 97

Abstract:

A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.

US Patent:

7894248, Feb 22, 2011

Filed:

Sep 12, 2008

Appl. No.:

12/210126

Inventors:

David Chang-Cheng Yu - Pleasanton CA, US
Xiao Luo - Cupertino CA, US

Assignee:

Grandis Inc. - Milpitas CA

International Classification:

G11C 11/00
G11C 17/00
G11C 17/02
G11C 11/14
G11C 17/18

US Classification:

365158, 365 96, 365 97, 365171, 3652257

Abstract:

Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and a sensing circuit coupled to the MTJ to sense a voltage under a breakdown condition of the MTJ.

US Patent:

7924287, Apr 12, 2011

Filed:

Jun 11, 2010

Appl. No.:

12/814306

Inventors:

David M. Blythe - San Carlos CA, US
Marc Schafer - Naples, IT
Paul Jeffrey Ungar - Mountain View CA, US
David Yu - San Francisco CA, US

Assignee:

Graphics Properties Holdings, Inc. - Palo Alto CA

International Classification:

G06F 15/80

US Classification:

345505, 345423, 345418

Abstract:

A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given subarea and a function of the rendering complexity for objects within this subarea. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the subareas. The cost of this approach is the necessity to communicate, in conjunction with each frame, the graphics data that will be rendered. Graphics data for a frame is composed of geometry chunks.

US Patent:

7952999, May 31, 2011

Filed:

May 8, 2007

Appl. No.:

11/745707

Inventors:

Dongyi Jiang - Milpitas CA, US
David Yu - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 29/02

US Classification:

370229, 370235

Abstract:

A device may receive packets for a system and obtain a packet drop rate of the system, a processor utilization rate of the system, and a target processor utilization rate of the system. In addition, the device may determine a target packet drop rate based on the packet drop rate, the processor utilization rate, and the target processor utilization rate. The device may drop a portion of the packets in accordance with the packet drop rate.