Dean W Stanford from 4563 Balmoral Park Ct, Fremont, CA 94538, age 60, Phone: 5106839186

Name / Title

Company / Classification

Phones & Addresses

Dean Stanford
Professional Engineer

Digital Power Corp
Electronic Components

41920 Christy St, Fremont, CA 94538

Dean Stanford
Professional Engineer

DIGITAL POWER CORPORATION
Mfg Cutting-Edge High-Grade Power System Solutions · Electronic Power Supplies-Manu · Other Electronic Component Manufacturing · Other Electronic Component Mfg

48430 Lakeview Blvd, Fremont, CA 94538
41324 Christy St, Fremont, CA 94538
41920 Christy St, Fremont, CA 94538
5106572635, 5106576634, 5103534023

Dean Stanford
President, Principal

ZERO EMISSIONS RECREATIONAL ORGANIZATION INC
Business Services at Non-Commercial Site · Nonclassifiable Establishments

4563 Balmoral Park Ct, Fremont, CA 94538

Us Patents

Test Head For Integrated Circuit Tester Arranging Tester Component Circuit Boards On Three Dimensions
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US Patent:

60406917, Mar 21, 2000
Filed:

May 23, 1997
Appl. No.:

8/862596
Inventors:

John C. Hanners - Brentwood CA
Charles A. Miller - Fremont CA
Dean Stanford - Fremont CA
Assignee:

Credence Systems Corporation - Fremont CA
International Classification:

G01R 3102
US Classification:

3241581
Abstract:

A test head for an integrated circuit tester includes a horizontal base holding a motherboard. The motherboard distributes test instructions to an array of daughterboards mounted thereon, the daughterboards being radially distributed about a central vertical axis of the motherboard. Each daughterboard holds a set of node cards and includes data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the daughterboards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board. The interface board extends those conductive paths from the pads to terminals of the DUT.

Test Head Structure For Integrated Circuit Tester
view source
US Patent:

59864478, Nov 16, 1999
Filed:

Mar 16, 1998
Appl. No.:

9/039738
Inventors:

John C. Hanners - Brentwood CA
Charles A. Miller - Fremont CA
Dean Stanford - Fremont CA
Assignee:

Credence Systems Corporation - Fremont CA
International Classification:

G01R 3102
US Classification:

3241581
Abstract:

A test head for an integrated circuit-tester includes a horizontal base holding a circular motherboard. The motherboard distributes input test instructions to an array of carrier boards mounted thereon, the carrier boards being radially distributed about a central vertical axis of the motherboard. Each carrier board holds a set of daughterboards, and each daughterboard holds a set of node cards. The carrier boards and daughterboards include data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the carrier boards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The carrier boards and daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board.