Deborah R Riley

US Patent:

7098099, Aug 29, 2006

Filed:

Feb 24, 2005

Appl. No.:

11/064583

Inventors:

Brian E. Hornung - Richardson TX, US
Jong Yoon - Plano TX, US
Deborah J. Riley - Richardson TX, US
Amitava Chatterjee - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238

US Classification:

438229, 438230, 438231, 438232, 438756

Abstract:

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). In one embodiment, the method includes growing an oxide layer from a substrate over a first dopant region and a second dopant region , implanting a first dopant through the oxide layer , into the substrate in the first dopant region , and adjacent a gate structure , and substantially removing the oxide layer from the substrate within the second dopant region. Subsequent to the removal of the oxide layer in the second dopant region , a second dopant that is opposite in type to the first dopant is implanted into the substrate and within the second dopant region and adjacent a gate structure.

US Patent:

7132365, Nov 7, 2006

Filed:

Aug 10, 2004

Appl. No.:

10/914928

Inventors:

Sue Ellen Crank - Coppell TX, US
Shirin Siddiqui - Plano TX, US
Deborah J. Riley - Richardson TX, US
Trace Quentin Hurd - Plano TX, US
Peijun J. Chen - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/4763

US Classification:

438648, 438630, 438664

Abstract:

A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

US Patent:

7323403, Jan 29, 2008

Filed:

Nov 29, 2004

Appl. No.:

10/999271

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Deborah J. Riley - Richardson TX, US
Trace Q. Hurd - Plano TX, US

Assignee:

Texas Instruments Incroporated - Dallas TX

International Classification:

H01L 21/3205
H01L 21/4763

US Classification:

438585, 438734, 257E21176, 257E21229

Abstract:

The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer () over a gate dielectric layer () located on a substrate (), and patterning the gate electrode layer () using a combination of a dry etch process () and a wet etch process ().

US Patent:

7371691, May 13, 2008

Filed:

Jul 29, 2004

Appl. No.:

10/901827

Inventors:

Lindsey H. Hall - Plano TX, US
Trace Q. Hurd - Plano TX, US
Deborah J. Riley - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/3065

US Classification:

438725

Abstract:

The present invention provides a process of manufacturing a semiconductor device while reducing silicon loss. In one aspect, the process includes removing a photoresist layer from a semiconductor substrate adjacent a gate and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer to a plasma ash. The plasma ash removes at least a portion of a crust formed on the photoresist layer but leaves a substantial portion of the photoresist layer. The photoresist layer is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer.

US Patent:

7384869, Jun 10, 2008

Filed:

Apr 7, 2005

Appl. No.:

11/100530

Inventors:

Deborah J. Riley - Richardson TX, US
Brian M. Trentman - Sherman TX, US
Brian K. Kirkpatrick - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438689, 438700, 438745, 257E21219, 257E21229, 257E21115, 257E21117, 257E21545

Abstract:

A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

US Patent:

7422969, Sep 9, 2008

Filed:

Sep 26, 2007

Appl. No.:

11/861392

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Deborah J. Riley - Richardson TX, US
Trace Q. Hurd - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/3205
H01L 21/4763

US Classification:

438585, 438734, 257E21176, 257E21229

Abstract:

The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer () over a gate dielectric layer () located on a substrate (), and patterning the gate electrode layer () using a combination of a dry etch process () and a wet etch process ().

US Patent:

7537988, May 26, 2009

Filed:

Oct 10, 2007

Appl. No.:

11/870241

Inventors:

Shashank Ekbote - Allen TX, US
Deborah J. Riley - Murphy TX, US
Borna Obradovic - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238
H01L 21/336

US Classification:

438199, 438230, 438267, 438302, 438303, 438304, 438738, 257E21431, 257E2164, 257E21626, 257E2163

Abstract:

A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.

US Patent:

7569464, Aug 4, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/615187

Inventors:

Karen H. R. Kirmse - Richardson TX, US
Yuanning Chen - Plano TX, US
Jarvis B. Jacobs - Murphy TX, US
Deborah J. Riley - Murphy TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/425

US Classification:

438514, 438230, 438301, 438303, 257E21002

Abstract:

The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.