Debra W Woolsey

US Patent:

20050167742, Aug 4, 2005

Filed:

Dec 29, 2004

Appl. No.:

11/026276

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Thomas Grebs - Mountaintop PA, US
Nathan Kraft - Pottsville PA, US
Dean Probst - West Jordan UT, US
Rodney Ridley - Mountaintop PA, US
Steven Sapp - Felton CA, US
Qi Wang - Sandy UT, US
Chongman Yun - Seoul City, KR
J.G. Lee - Puchon-Si, KR
Peter Wilson - Wrightwood CA, US
Joseph Yedinak - Mountaintop PA, US
J.Y. Jung - Kyunggi-do, KR
H.C. Jang - Kyoungki-do, KR
Babak Sani - Oakland CA, US
Richard Stokes - Shavertown PA, US
Gary Dolny - Mountaintop PA, US
John Mytych - Mohnton PA, US
Becky Losee - Cedar Hills UT, US
Adam Selsley - Mountaintop PA, US
Robert Herrick - Lehi UT, US
James Murphy - South Jordan UT, US
Gordon Madson - Riverton UT, US
Bruce Marchant - Murray UT, US
Christopher Rexer - Mountaintop PA, US
Christopher Kocon - Plains PA, US
Debra Woolsey - Draper UT, US

Assignee:

Fairchild Semiconductor Corp. - South Portland ME

International Classification:

G06F001/26

US Classification:

257328000

Abstract:

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

US Patent:

20080138953, Jun 12, 2008

Filed:

Feb 15, 2008

Appl. No.:

12/032599

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Dean E. Probst - West Jordan UT, US
Steven P. Sapp - Felton CA, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Becky Losee - Cedar Hills UT, US
Robert Herrick - Lehi UT, US
James J. Murphy - South Jordan UT, US
Gordon K. Madson - Riverton UT, US
Bruce D. Marchant - Murray UT, US
Christopher B. Kocon - Plains PA, US
Debra S. Woolsey - Draper UT, US

International Classification:

H01L 21/336
H01L 21/762

US Classification:

438270, 438437, 257E2141, 257E21546

Abstract:

A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

US Patent:

20080199995, Aug 21, 2008

Filed:

Feb 15, 2007

Appl. No.:

11/675596

Inventors:

Debra Susan Woolsey - Draper UT, US
Joelle Sharp - Herriman UT, US
Tony Lane Olsen - Riverton UT, US
Gordon K. Madson - Herriman UT, US

International Classification:

H01L 21/336

US Classification:

438259, 438270, 257E2141, 257E21421

Abstract:

A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.

US Patent:

20100187602, Jul 29, 2010

Filed:

Jan 29, 2009

Appl. No.:

12/362321

Inventors:

Debra S. Woolsey - Salt Lake City UT, US
Tony L. Olsen - Salt Lake City UT, US
Gordon K. Madson - Salt Lake City UT, US

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257330, 438589, 257E2141, 257E29262

Abstract:

Semiconductor devices and methods for making such devices using nitride consumption LOCOS oxidation are described. The semiconductor devices contain a planar field oxide structure that has been grown using a nitride layer as an oxidation mask. Once the field oxide structure has been grown, the nitride mask is not etched away, but rather converted to an oxide layer by an oxidation process using radicals of hydrogen and oxygen. The semiconductor devices also contain a shielded gate trench MOSFET that can be created using an oxide layer with an overlying nitride layer as the channel (sidewall) gate dielectric. An inter-poly-dielectric (IPD) layer can be formed from a thermally grown oxide which uses the nitride layer as a oxidation mask. The thickness of the IPD layer can be adjusted to any thickness needed with minimal effect of the channel gate dielectric layer. An oxidation process using radicals of hydrogen and oxygen can be preformed to consume the nitride layer and form the gate oxide in the channel region. Since the gate channel nitride acts as a barrier to the oxidation, the IPD oxide layer can be grown to any needed thickness with minimal oxidation to the channel gate and the nitride layer can be removed without any etching processes. Other embodiments are described.

US Patent:

20120220091, Aug 30, 2012

Filed:

Mar 12, 2012

Appl. No.:

13/418128

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Thomas E. Grebs - , US
Nathan L. Kraft - , US
Dean E. Probst - West Jordan UT, US
Rodney S. Ridley - , US
Steven P. Sapp - Felton CA, US
Qi Wang - , US
Chongman Yun - , US
Peter H. Wilson - Wrightwood CA, US
Joseph A. Yedinak - , US
Babak S. Sani - Oakland CA, US
Richard Stokes - , US
Gary M. Dolny - , US
John Mytych - , US
Becky Losee - Cedar Hills UT, US
Adam Selsley - , US
Robert Herrick - Lehi UT, US
James J. Murphy - South Jordan UT, US
Gordon K. Madson - Riverton UT, US
Bruce D. Marchant - Murray UT, US
Christopher L. Rexer - , US
Christopher B. Kocon - Murray PA, US
Debra S. Woolsey - Draper UT, US

International Classification:

H01L 21/336
H01L 21/311

US Classification:

438270, 438694, 438703, 257E21249, 257E21419

Abstract:

A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.