Deepak Kumar Gupta

US Patent:

20220283813, Sep 8, 2022

Filed:

Jun 26, 2021

Appl. No.:

17/359534

Inventors:

- Santa Clara CA, US
H. Peter Anvin - San Jose CA, US
Vedvyas Shanbhogue - Austin TX, US
Deepak Gupta - Portland OR, US

International Classification:

G06F 9/30

Abstract:

Techniques for flexible return and event delivery are described. As an example, an exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded single instruction according to the opcode to cause a return from an event handler while staying in a most privileged level and establish a return context that was in effect before event delivery.

US Patent:

20230043506, Feb 9, 2023

Filed:

Jul 26, 2022

Appl. No.:

17/873668

Inventors:

DAVID M. DURHAM - Beaverton OR, US
JACOB DOWECK - Haifa, IL
MICHAEL LEMAY - Hillsboro OR, US
DEEPAK GUPTA - Portland OR, US

International Classification:

G06F 12/1027

Abstract:

An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

US Patent:

20210382987, Dec 9, 2021

Filed:

Aug 19, 2021

Appl. No.:

17/407035

Inventors:

Vedvyas Shanbhogue - Austin TX, US
Jason W. Brandt - Austin TX, US
Ravi L. Sahita - Beaverton OR, US
Barry E. Huntley - Hillsboro OR, US
Baiju V. Patel - Portland OR, US
Deepak K. Gupta - Hillsboro OR, US

International Classification:

G06F 21/52
G06F 3/06
G06F 12/14
G06F 9/30
G06F 9/46

Abstract:

A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

US Patent:

20210357213, Nov 18, 2021

Filed:

Jun 7, 2021

Appl. No.:

17/340632

Inventors:

- Santa Clara CA, US
Jason W. Brandt - Austin TX, US
Ravi L. Sahita - Beaverton OR, US
Barry E. Huntley - Hillsboro OR, US
Baiju V. Patel - Portland OR, US
Deepak K. Gupta - Hillsboro OR, US

International Classification:

G06F 9/30
G06F 9/46
G06F 21/52

Abstract:

Methods and apparatuses relating to switching of a shadow stack pointer are described. In one embodiment, a hardware processor includes a hardware decode unit to decode an instruction, and a hardware execution unit to execute the instruction to: pop a token for a thread from a shadow stack, wherein the token includes a shadow stack pointer for the thread with at least one least significant bit (LSB) of the shadow stack pointer overwritten with a bit value of an operating mode of the hardware processor for the thread, remove the bit value in the at least one LSB from the token to generate the shadow stack pointer, and set a current shadow stack pointer to the shadow stack pointer from the token when the operating mode from the token matches a current operating mode of the hardware processor.

US Patent:

20210311883, Oct 7, 2021

Filed:

May 14, 2021

Appl. No.:

17/321087

Inventors:

- Santa Clara CA, US
JACOB DOWECK - Haifa, IL
MICHAEL LEMAY - Hillsboro OR, US
DEEPAK GUPTA - Portland OR, US

International Classification:

G06F 12/1027

Abstract:

An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

US Patent:

20210303304, Sep 30, 2021

Filed:

Mar 28, 2020

Appl. No.:

16/833599

Inventors:

- Santa Clara CA, US
Gilbert NEIGER - Portland OR, US
Deepak K. GUPTA - Portland OR, US
H. Peter ANVIN - San Jose CA, US

International Classification:

G06F 9/30
G06F 9/48
G06F 9/54
G06F 16/176

Abstract:

An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs), each SSP associated with a different event priority; event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete, and wherein if the first SSP has been previously verified, then re-verifying the first SSP and confirming that the first SSP is not in use without using the locking operation.

US Patent:

20200159673, May 21, 2020

Filed:

Nov 18, 2019

Appl. No.:

16/686379

Inventors:

- Santa Clara CA, US
GILBERT NEIGER - Hillsboro OR, US
VEDVYAS SHANBHOGUE - Austin TX, US
DAVID M. DURHAM - Beaverton OR, US
ANDREW V. ANDERSON - Forest Grove OR, US
DAVID A. KOUFATY - Portland OR, US
ASIT K. MALLICK - Saratoga CA, US
ARUMUGAM THIYAGARAJAH - Folsom CA, US
BARRY E. HUNTLEY - Hillsboro OR, US
DEEPAK K. GUPTA - Hillsboro OR, US
MICHAEL LEMAY - Hillsboro OR, US
JOSEPH F. CIHULA - Hillsboro OR, US
BAIJU V. PATEL - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/14
G06F 9/455
G06F 12/1009
G06F 12/1027

Abstract:

This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

US Patent:

20200089871, Mar 19, 2020

Filed:

Sep 27, 2019

Appl. No.:

16/585373

Inventors:

- Santa Clara CA, US
Jason W. Brandt - Austin TX, US
Ravi L. Sahita - Beaverton OR, US
Barry E. Huntley - Hillsboro OR, US
Baiju V. Patel - Portland OR, US
Deepak K. Gupta - Hillsboro OR, US

International Classification:

G06F 21/52
G06F 3/06
G06F 12/14
G06F 9/30
G06F 9/46

Abstract:

A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.