Denise S Man

US Patent:

6765295, Jul 20, 2004

Filed:

Apr 23, 2003

Appl. No.:

10/421499

Inventors:

Elias Gedamu - Calgary, CA
Denise Man - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 2348

US Classification:

257754, 257211, 257758

Abstract:

Systems and methods are described for sharing signals across a common metal trace on a single metal layer of an integrated circuit. The signals are time division multiplexed across the common metal trace such that a single metal layer of an integrated circuit is used to multiplex signals to and from a poly-silicon layer, reducing utilization of upper metal layers of the integrated circuit.

US Patent:

6961674, Nov 1, 2005

Filed:

Aug 11, 2003

Appl. No.:

10/638561

Inventors:

Elias Gedamu - Calgary, CA
Denise Man - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F011/00

US Classification:

702183, 324 731

Abstract:

One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period of time for a second plurality of storage elements; determining a plurality of attributes for each of the first storage elements and the second storage elements based upon the test results, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determining a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generating an output report indicating at least two of the attribute statistics of the first storage elements and the second storage elements.

US Patent:

6969952, Nov 29, 2005

Filed:

Aug 1, 2003

Appl. No.:

10/633000

Inventors:

Eilas Gedamu - Calgary, CA
Denise Man - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50
H01L027/10

US Classification:

315 94, 716 12, 257206

Abstract:

A system for automatically routing power in an integrated circuit, the system comprising memory for storing data defining a representation of an integrated circuit having a power contact and a power connection, and logic configured to analyze the data and to automatically route power from the power connection to the power contact.

US Patent:

6975945, Dec 13, 2005

Filed:

Aug 26, 2003

Appl. No.:

10/649404

Inventors:

Elias Gedamu - Calgary, CA
Denise Man - Fort Collins CO, US

Assignee:

Hewlett Packard Development Company, L.P. - Houston TX

International Classification:

G01R031/00
G01B005/28

US Classification:

702 59, 702 35, 702 36

Abstract:

One embodiment of a method comprises retrieving test data corresponding to test results from a plurality of fuses, each one of the plurality of fuses residing on a different one of a plurality of semiconductor devices and each one of the plurality of fuses having a common location on the semiconductor devices, determining from the test data which of the plurality of fuses are defective fuses, and specifying on an output report the common location of the determined defective fuses when a number of the defective fuses are at least equal to a predefined portion of the plurality of fuses.

US Patent:

7818645, Oct 19, 2010

Filed:

Jul 20, 2005

Appl. No.:

11/185291

Inventors:

Elias Gedamu - Montreal, CA
Denise Man - Fort Collins CO, US
Eric Richard Stubblefield - Fort Collins CO, US
Oguz Ertekin - San Mateo CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 31/28
G06F 11/00
G06F 13/00

US Classification:

714733, 714 28, 714 30, 714736, 711114, 711128

Abstract:

Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

US Patent:

20050039089, Feb 17, 2005

Filed:

Aug 11, 2003

Appl. No.:

10/638568

Inventors:

Elias Gedamu - Calgary, CA
Denise Man - Fort Collins CO, US

International Classification:

G11C029/00

US Classification:

714718000

Abstract:

One embodiment of a method for analysis of cache array test data comprises retrieving cache array test data corresponding to test results of at least one cache array, analyzing the cache array test data, determining a condition of the cache array based upon the cache array test data, and generating an output report indicating a location the determined cache array on a wafer.

US Patent:

20050188334, Aug 25, 2005

Filed:

Feb 24, 2004

Appl. No.:

10/785748

Inventors:

Gaurav Shah - Caldwell ID, US
Denise Man - Fort Collins CO, US

International Classification:

G06F017/50

US Classification:

716001000

Abstract:

One example embodiment of an interface arrangement for retrieving circuit design data comprises a first application program callable function configured to, in response to an application programming interface (API) call to the first function that specifies a block, read design data related to the block in a first format and store the design data in a second format different from the first. The interface arrangement further comprises a second application program callable function configured to, in response to an API call to the second function requesting block characteristics from the design data stored in the second format, access the stored design data in the second format and return information regarding characteristics of the specified block.

US Patent:

20050251766, Nov 10, 2005

Filed:

May 7, 2004

Appl. No.:

11/089572

Inventors:

Gaurav Shah - Caldwell ID, US
Denise Man - Fort Collins CO, US

International Classification:

G06F017/50

US Classification:

716004000, 716007000, 716011000, 703016000

Abstract:

According to an example embodiment of an approach to circuit design processing involves using an interface for retrieving and processing circuit design data for use by a plurality of simulation tools. The interface includes an application program callable function configured to return functional classification data in response to an application programming interface (API) call from a simulation tool. The API call specifies a design block identifier that is used by the application program callable function to search a data source for functional classification data associated with the design block identifier. If functional classification data associated with the design block identifier is not found in the data source, a plurality of circuit elements associated with the design block identifier is retrieved from a netlist. A functional classification of the plurality of circuit elements is determined and functional classification data indicative of the functional classification is associated with the design block identifier and stored in the data source. Functional classification data associated with the design block identifier is also returned to the simulation tool.