Dennis C Blankenship

US Patent:

7180911, Feb 20, 2007

Filed:

Aug 14, 2002

Appl. No.:

10/218796

Inventors:

Dennis N. Blankenship - Holly Springs NC, US
Thomas W. Scheviak - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 3/24
H04L 12/56

US Classification:

370473, 370413, 370535, 710313, 710100

Abstract:

A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet handle, interface handle, and data packet are communicated to a second processor. A plurality of data packets that are destined for the same output are multiplexed. At least one packet handle, one interface handle, and the multiplexed data packet are communicated to the first processor, and the multiplexed data packet is output.

US Patent:

7237182, Jun 26, 2007

Filed:

Dec 12, 2003

Appl. No.:

10/735383

Inventors:

Dennis N. Blankenship - Holly Springs NC, US
John S. Morris - Raleigh NC, US
Walter L. Robinson - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H03M 3/00

US Classification:

714781, 714758

Abstract:

A method for selective recovery in a communications environment is provided that includes building a recognizable bit pattern into one or more subframes that are associated with a communication flow. One or more of the subframes may be positioned into a superframe. In cases where one or more errors are present in the superframe, the superframe may be demultiplexed such that one or more of the subframes included in the superframe are analyzed and then discarded or forwarded based on the presence of one or more of the errors.

US Patent:

7248560, Jul 24, 2007

Filed:

Jun 4, 2002

Appl. No.:

10/162776

Inventors:

Dennis N. Blankenship - Holly Springs NC, US
Michael H. Otto - Apex NC, US
Peter D. Beal - Apex NC, US
John M. Glotzer - Chapel Hill NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/08

US Classification:

370220, 370219, 370328, 370401

Abstract:

A method for selecting an active router in a communication device includes providing multiple routers in the device, coupling the routers to a single physical link, monitoring a status for each of the routers, and selecting one of the routers as an active router by positioning its corresponding relay.

US Patent:

7453900, Nov 18, 2008

Filed:

Mar 5, 2003

Appl. No.:

10/382711

Inventors:

Walter L. Robinson - Raleigh NC, US
Peter D. Beal - Apex NC, US
Dennis N. Blankenship - Holly Springs NC, US
Sumita Bose - Cary NC, US
Bohdan Matuszczak - Morrisville NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370431

Abstract:

A method for monitoring noise associated with a communication link is provided that includes monitoring a plurality of communication links that facilitate a plurality of communication flows and determining whether an error parameter associated with a selected one or more of the communication links has exceeded a predefined threshold. An alert message may then be communicated to a next destination when the predefined threshold has been exceeded.

US Patent:

7554903, Jun 30, 2009

Filed:

Jul 24, 2007

Appl. No.:

11/782029

Inventors:

Dennis N. Blankenship - Holly Springs NC, US
Michael H. Otto - Apex NC, US
Peter D. Beal - Apex NC, US
John M. Glotzer - Chapel Hill NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/08

US Classification:

370220, 370219, 370328

Abstract:

A method for selecting an active router in a communication device includes providing multiple routers in the device, coupling the routers to a single physical link, monitoring a status for each of the routers, and selecting one of the routers as an active router by positioning its corresponding relay.

US Patent:

7616651, Nov 10, 2009

Filed:

Feb 19, 2007

Appl. No.:

11/676367

Inventors:

Dennis N. Blankenship - Holly Springs NC, US
Thomas W. Scheviak - Raleigh NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370412, 711147

Abstract:

A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet handle, interface handle, and data packet are communicated to a second processor. A plurality of data packets that are destined for the same output are multiplexed. At least one packet handle, one interface handle, and the multiplexed data packet are communicated to the first processor, and the multiplexed data packet is output.

US Patent:

7872936, Jan 18, 2011

Filed:

Sep 17, 2008

Appl. No.:

12/212400

Inventors:

Dennis Blankenship - Cary NC, US

Assignee:

Qimonda AG - München

International Classification:

G11C 8/00

US Classification:

36523003, 36523001, 36518904, 36523311, 36518919, 365201

Abstract:

In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.

US Patent:

54867851, Jan 23, 1996

Filed:

Sep 30, 1994

Appl. No.:

8/316462

Inventors:

Dennis R. Blankenship - Durham NC

Assignee:

Mitsubishi Semiconductor America, Inc. - Durham NC

International Classification:

H03L 500

US Classification:

327306

Abstract:

A level shift circuit provided with feedforward control to keep the circuit from latching in a wrong logic state comprises a pair of input transistors acted as a differential amplifier and a pair of output hold transistors coupled to output nodes of the circuit. The feedforward control is performed by a pair of feedforward transistors respectively coupled in parallel to the corresponding output hold transistors, and by a pair of isolation transistors that isolate the output nodes from gates of the respective feedforward transistors.