Dennis E Robinson

US Patent:

53961153, Mar 7, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/149245

Inventors:

Tim M. Coffman - Sugar Land TX
Phat C. Truong - Houston TX
T. Damodar Reddy - Nalgonda, IN
Dennis R. Robinson - Needville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1722

US Classification:

327143

Abstract:

The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

US Patent:

54249929, Jun 13, 1995

Filed:

Aug 25, 1993

Appl. No.:

8/112484

Inventors:

Tim M. Coffman - Sugar Land TX
Dennis R. Robinson - Needville TX
Phat C. Truong - Houston TX
T. Damodar Reddy - Nalgonda, IN

Assignee:

Texas Instruments Incorporated, a Delaware corporation - Dallas TX

International Classification:

G11C 1300

US Classification:

365218

Abstract:

An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL. sub. --). The higher voltage level bias signal (ECL. sub. --) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM. sub. --) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM. sub. --) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.