Derek Martin

US Patent:

20210397718, Dec 23, 2021

Filed:

Aug 31, 2021

Appl. No.:

17/462698

Inventors:

- Mountain View CA, US
Timothy Chen - Mountain View CA, US
Scott D. Johnson - Cupertino CA, US
Derek L. Martin - Chandler AZ, US

Assignee:

Google LLC - Mountain View CA

International Classification:

G06F 21/57
H04L 9/06
G06F 21/56
G06F 21/51

Abstract:

Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

US Patent:

20190163909, May 30, 2019

Filed:

Jan 30, 2019

Appl. No.:

16/262179

Inventors:

- Mountain View CA, US
Timothy CHEN - Mountain View CA, US
Scott JOHNSON - Mountain View CA, US
Harrison PHAM - Mountain View CA, US
Derek MARTIN - Mountain View CA, US

Assignee:

Google LLC - Mountain View CA

International Classification:

G06F 21/57
G01R 31/3185
H04L 9/08
G06F 21/30
G01R 31/317
G06F 21/73
G06F 21/74
G06F 21/75
G11C 29/46
G11C 29/40
G11C 29/36
G11C 16/22
G11C 7/24
G06F 21/79

Abstract:

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.

US Patent:

20180253557, Sep 6, 2018

Filed:

Feb 19, 2018

Appl. No.:

15/898858

Inventors:

- Mountain View CA, US
Timothy Chen - Mountain View CA, US
Scott D. Johnson - Cupertino CA, US
Derek L. Martin - Chandler AZ, US

Assignee:

Google LLC - Mountain View CA

International Classification:

G06F 21/57
G06F 21/56
H04L 9/06

Abstract:

Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

US Patent:

20180189493, Jul 5, 2018

Filed:

Dec 30, 2016

Appl. No.:

15/396052

Inventors:

- Mountain View CA, US
Timothy CHEN - Mountain View CA, US
Scott JOHNSON - Mountain View CA, US
Harrison PHAM - Mountain View CA, US
Derek MARTIN - Mountain View CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 21/57
G06F 21/30
H04L 9/08

Abstract:

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.