Derrick Sai Tang Butt from 112 Woodland Valley Dr, San Ramon, CA 94582, age 55, Phone: 9259999212

Resumes

Derrick Butt

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Us Patents

Programmable Data Strobe Enable Architecture For Ddr Memory Applications
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US Patent:

7394707, Jul 1, 2008
Filed:

Jun 24, 2005
Appl. No.:

11/166292
Inventors:

Hui-Yin Seto - San Jose CA, US
Derrick Sai-Tang Butt - San Leandro CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G11C 7/00
US Classification:

365193, 365233, 365194
Abstract:

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

Configurable High-Speed Memory Interface Subsystem
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US Patent:

7437500, Oct 14, 2008
Filed:

Aug 5, 2005
Appl. No.:

11/198416
Inventors:

Derrick Sai-Tang Butt - San Leandro CA, US
Cheng-Gang Kong - Saratoga CA, US
Terence J. Magee - San Francisco CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G06F 12/00
US Classification:

711105, 711 4, 711100, 711106, 711111, 365189011, 36518901, 36518902, 36518903, 36518904, 36518905, 36518914, 36518915, 36518916, 36518917, 36518918, 365191, 365193, 365194, 365195, 365223, 36523311, 36523313
Abstract:

A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

Dqs Strobe Centering (Data Eye Training) Method
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US Patent:

7443741, Oct 28, 2008
Filed:

Jul 7, 2005
Appl. No.:

11/176041
Inventors:

Derrick Sai-Tang Butt - San Leandro CA, US
Hui-Yin Seto - San Jose CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G11C 7/00
US Classification:

365193, 365201, 365174
Abstract:

A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a read data strobe signal based upon the base delay and the optimum offset delay value for each of the one or more datapaths.

Configurable High-Speed Memory Interface Subsystem
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US Patent:

7865661, Jan 4, 2011
Filed:

Oct 13, 2008
Appl. No.:

12/250017
Inventors:

Derrick Sai-Tang Butt - San Leandro CA, US
Cheng-Gang Kong - Saratoga CA, US
Terence J. Magee - San Francisco CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G06F 12/00
US Classification:

711105, 711 4, 711100, 711111, 711106, 36518918, 36518902, 36518903, 36518904, 36518905, 36518914, 36518915, 36518916, 36518917, 365191, 365192, 365193, 365194, 365195, 36523311, 36523313
Abstract:

A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Multiple Memory Standard Physical Layer Macro Function
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US Patent:

7969799, Jun 28, 2011
Filed:

Apr 25, 2008
Appl. No.:

12/109643
Inventors:

Derrick Sai-Tang Butt - San Leandro CA, US
Cheng-Gang Kong - Saratoga CA, US
Terence J. Magee - San Francisco CA, US
Thomas Hughes - San Francisco CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G11C 7/10
G11C 7/00
G11C 8/00
G11C 8/18
US Classification:

36518916, 36518905, 36518914, 36523313, 36523316
Abstract:

A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

System For Terminating High Speed Input/Output Buffers In An Automatic Test Equipment Environment To Enable External Loopback Testing
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US Patent:

8098073, Jan 17, 2012
Filed:

Sep 27, 2007
Appl. No.:

11/862451
Inventors:

Derrick Sai-Tang Butt - San Leandro CA, US
David Carkeek - Saratoga CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G01R 31/02
US Classification:

324537
Abstract:

An apparatus comprising a test termination card having a first set of connections and a second set of connections. The first set of connections may be configured to connect to a specific pinout of a device under test. The second set of connections may be configured to connect to a general pinout of a tester load board. The termination card may toggle between (a) connecting the first set of connectors to the second set of connectors to implement a first test type and (b) disconnecting the first set of connectors from the second set of connectors to implement a second test type.

Macro Cell For Integrated Circuit Physical Layer Interface
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US Patent:

20050229132, Oct 13, 2005
Filed:

Mar 26, 2004
Appl. No.:

10/810294
Inventors:

Derrick Butt - San Leandro CA, US
Bruce Cochrane - San Jose CA, US
Hui Seto - San Jose CA, US
William Lau - Foster City CA, US
Thomas McCarthy - Cary NC, US
Assignee:

LSI Logic Corporation - Milpitas CA
International Classification:

G06F017/50
US Classification:

716010000
Abstract:

A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.

Feedback Programmable Data Strobe Enable Architecture For Ddr Memory Applications
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US Patent:

20060288175, Dec 21, 2006
Filed:

Jun 16, 2005
Appl. No.:

11/154401
Inventors:

Hui-Yin Seto - San Jose CA, US
Derrick Butt - San Leandro CA, US
Cheng-Gang Kong - Saratoga CA, US
International Classification:

G06F 13/00
US Classification:

711154000, 711105000
Abstract:

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.