Dibakar Gope

age ~38

from Austin, TX

Also known as:
  • Gope Dibakar
  • Gopi Dibakar

Dibakar Gope Phones & Addresses

  • Austin, TX
  • Madison, WI
  • College Station, TX
  • Sunnyvale, CA
  • Sioux Falls, SD

Us Patents

  • Mixed-Element-Size Instruction

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  • US Patent:
    20210389948, Dec 16, 2021
  • Filed:
    Jun 10, 2020
  • Appl. No.:
    16/897483
  • Inventors:
    - Cambridge, GB
    Dibakar GOPE - Austin TX, US
    David Hennah MANSELL - Norwich, GB
  • International Classification:
    G06F 9/30
  • Abstract:
    A mixed-element-size instruction is described, which specifies a first operand and a second operand stored in registers. In response to the mixed-element-size instruction, an instruction decoder controls processing circuitry to perform an arithmetic/logical operation on two or more first data elements of the first operand and two or more second data elements of the second operand, where the first data elements have a larger data element size than the second data elements. This is particularly useful for machine learning applications to improve processing throughput and memory bandwidth utilisation.
  • Scoped Persistence Barriers For Non-Volatile Memories

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  • US Patent:
    20190286362, Sep 19, 2019
  • Filed:
    Jun 5, 2019
  • Appl. No.:
    16/432391
  • Inventors:
    - Santa Clara CA, US
    Mitesh R. Meswani - Austin TX, US
    Dibakar Gope - Madison WI, US
    Sooraj Puthoor - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Santa Clara CA
  • International Classification:
    G06F 3/06
    G06F 12/02
  • Abstract:
    A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
  • Scoped Persistence Barriers For Non-Volatile Memories

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  • US Patent:
    20180088858, Mar 29, 2018
  • Filed:
    Sep 23, 2016
  • Appl. No.:
    15/274777
  • Inventors:
    - Sunnyvale CA, US
    Mitesh R. Meswani - Austin TX, US
    Dibakar Gope - Madison WI, US
    Sooraj Puthoor - Austin TX, US
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G06F 3/06
    G06F 12/0804
  • Abstract:
    A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
  • Apparatus And Method For Bias-Free Branch Prediction

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  • US Patent:
    20150363203, Dec 17, 2015
  • Filed:
    Jun 13, 2014
  • Appl. No.:
    14/303932
  • Inventors:
    - Madison WI, US
    Dibakar Gope - Madison WI, US
  • International Classification:
    G06F 9/38
    G06F 9/30
  • Abstract:
    Aspects of the present invention provide an apparatus and method for filtering biased conditional branches in a branch predictor in favor of non-biased conditional branches. Biased conditional branches, which are consistently skewed toward one direction or outcome, are filtered such that an increased number of non-biased conditional branches which resolve in both directions may be considered. As a result, more useful branches may be captured over larger distances, thereby providing correlations deeper in a global history to provide greater prediction accuracy. In addition, by tracking only the latest occurrences of non-biased conditional branches using a recency stack structure, even more distant branch correlations may be made.

Resumes

Dibakar Gope Photo 1

Design Engineer

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Location:
Austin, TX
Industry:
Computer Hardware
Work:
Arm
Senior Research Engineer, Machine Learning and Ai

Amd Jun 2015 - Dec 2015
Co-Op Engineer, Amd Research

Freescale Semiconductor Jun 2015 - Dec 2015
Design Engineer
Education:
University of Wisconsin - Madison 2011 - 2016
Doctorates, Doctor of Philosophy, Architecture
University of Wisconsin - Madison 2010 - 2014
Doctorates, Doctor of Philosophy
Texas A&M University 2009 - 2011
Master of Science, Masters, Computer Engineering
Birla Institute of Technology and Science, Pilani 2004 - 2008
Bachelor of Engineering, Bachelors, Electronics Engineering
Dibakar Gope Photo 2

Dibakar Gope

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Googleplus

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Dibakar Gope

Facebook

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Dibakar Gope

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Dibakar Gope Photo 5

Dibakar Gope

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Dibakar Gope Photo 6

Dibakar Gope

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Other Social Networks

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Dibakar Gope Google+

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Network:
GooglePlus
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