Dimitri A Antoniadis

US Patent:

6573126, Jun 3, 2003

Filed:

Aug 10, 2001

Appl. No.:

09/928126

Inventors:

Zhi-Yuan Cheng - Cambridge MA
Eugene A. Fitzgerald - Windham NH
Dimitri A. Antoniadis - Newton MA
Judy L. Hoyt - Belmont MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 2100

US Classification:

438149, 438933

Abstract:

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si Ge (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si Ge layer, a thin strained Si Ge layer and another relaxed Si Ge layer. Hydrogen ions are then introduced into the strained Si Ge layer. The relaxed Si Ge layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si Ge layer remains on the second substrate. In another exemplary embodiment, a graded Si Ge is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.

US Patent:

6713326, Mar 30, 2004

Filed:

Mar 4, 2003

Appl. No.:

10/379355

Inventors:

Zhi-Yuan Cheng - Cambridge MA
Eugene A. Fitzgerald - Windham NH
Dimitri A. Antoniadis - Newton MA
Judy L. Hoyt - Belmont MA

Assignee:

Masachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 2100

US Classification:

438149

Abstract:

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si Ge (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si Ge layer, a thin strained Si Ge layer and another relaxed Si Ge layer. Hydrogen ions are then introduced into the strained Si Ge layer. The relaxed Si Ge layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si Ge layer remains on the second substrate. In another exemplary embodiment, a graded Si Ge is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.

US Patent:

6737670, May 18, 2004

Filed:

Mar 7, 2003

Appl. No.:

10/384160

Inventors:

Zhi-Yuan Cheng - Cambridge MA
Eugene A. Fitzgerald - Windham NH
Dimitri A. Antoniadis - Newton MA
Judy L. Hoyt - Belmont MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 2906

US Classification:

257 19

Abstract:

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si Ge (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si Ge layer, a thin strained Si Ge layer and another relaxed Si Ge layer. Hydrogen ions are then introduced into the strained Si Ge layer. The relaxed Si Ge layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si Ge layer remains on the second substrate. In another exemplary embodiment, a graded Si Ge is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.

US Patent:

6921914, Jul 26, 2005

Filed:

Mar 17, 2004

Appl. No.:

10/802185

Inventors:

Zhi-Yuan Cheng - Cambridge MA, US
Eugene A. Fitzgerald - Windham NH, US
Dimitri A. Antoniadis - Newton MA, US
Judy L. Hoyt - Belmont MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L029/06
H01L031/0328
H01L031/0336
H01L031/072
H01L031/109

US Classification:

257 19, 257 55, 257 63, 257 65, 257200, 257616

Abstract:

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded SiGe(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed SiGelayer, a thin strained SiGelayer and another relaxed SiGelayer. Hydrogen ions are then introduced into the strained SiGelayer. The relaxed SiGelayer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed SiGelayer remains on the second substrate. In another exemplary embodiment, a graded SiGeis deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.

US Patent:

6940089, Sep 6, 2005

Filed:

Apr 4, 2002

Appl. No.:

10/116559

Inventors:

Zhiyuan Cheng - Cambridge MA, US
Eugene A. Fitzgerald - Windham NH, US
Dimitri A. Antoniadis - Newton MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L029/06
H01L031/0328
H01L031/0336
H01L031/072
H01L029/04

US Classification:

257 19, 257 55

Abstract:

A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded SiGebuffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop SiGelayer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop SiGelayer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed.

US Patent:

6991972, Jan 31, 2006

Filed:

Oct 22, 2003

Appl. No.:

10/691007

Inventors:

Anthony J. Lochtefeld - Somerville MA, US
Dimitri Antoniadis - Newton MA, US
Matthew T. Currie - Windham NH, US

Assignee:

AmberWave Systems Corporation - Salem NH

International Classification:

H01L 21/00
H01L 27/01

US Classification:

438149, 438150, 438198, 438938, 257347, 257350, 257351

Abstract:

In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

US Patent:

7074655, Jul 11, 2006

Filed:

Sep 28, 2005

Appl. No.:

11/237175

Inventors:

Anthony J. Lochtefeld - Somerville MA, US
Dimitri Antoniadis - Newton MA, US
Matthew T. Currie - Brookline MA, US

Assignee:

AmberWave Systems Corporation - Salem NH

International Classification:

H01L 21/00
H01L 27/01

US Classification:

438149, 438150, 438198, 438938, 257347, 257350, 257351

Abstract:

In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

US Patent:

7304336, Dec 4, 2007

Filed:

Feb 13, 2004

Appl. No.:

10/778953

Inventors:

Zhiyuan Cheng - Cambridge MA, US
Eugene A. Fitzgerald - Windham NH, US
Dimitri Antoniadis - Newton MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 29/76
H01L 29/32

US Classification:

257288, 257289, 257327, 257E29022, 257E29105

Abstract:

A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.