Dinesh Kumar Gupta

US Patent:

7926011, Apr 12, 2011

Filed:

Jan 10, 2007

Appl. No.:

11/621915

Inventors:

Oleg Levitsky - San Jose CA, US
Chien-Chu Kuo - San Jose CA, US
Dinesh Gupta - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716105, 716103, 716104, 716106, 716113, 716117, 716134, 716138, 716139

Abstract:

A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

US Patent:

8365113, Jan 29, 2013

Filed:

Feb 18, 2010

Appl. No.:

12/708530

Inventors:

Vivek Bhardwaj - New Delhi, IN
Oleg Levitsky - San Jose CA, US
Dinesh Gupta - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106, 716104, 716105, 716108, 716113, 716118, 716124, 716132, 716134, 716139

Abstract:

In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

US Patent:

8539402, Sep 17, 2013

Filed:

Dec 15, 2012

Appl. No.:

13/716129

Inventors:

Vivek Bhardwaj - New Delhi, IN
Oleg Levitsky - San Jose CA, US
Dinesh Gupta - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716105, 716106, 716108, 716113, 716118, 716124, 716132, 716134, 716139

Abstract:

In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

US Patent:

8640066, Jan 28, 2014

Filed:

Oct 4, 2010

Appl. No.:

12/897777

Inventors:

Dinesh Gupta - Sunnyvale CA, US
Oleg Levitsky - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716108, 716102, 716103, 716105, 716106, 716110, 716111, 716113, 716122, 716124, 716136

Abstract:

In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.