Dinesh Mv Rao

US Patent:

56491425, Jul 15, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/476061

Inventors:

Gary Lavelle - Newtown PA
Louis A. Lippincott - Roebling NJ
Kevin Harney - Brooklyn NY
Dinesh G. Rao - Rancho Cordova CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1210
G06F 1300

US Classification:

395419

Abstract:

A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address.