Dipak Kumar Sikdar

US Patent:

8451675, May 28, 2013

Filed:

Mar 31, 2011

Appl. No.:

13/077811

Inventors:

Richard S. Roy - Dublin CA, US
Dipak K. Sikdar - Santa Clara CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365203, 36518916, 36518908

Abstract:

A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

US Patent:

8547774, Oct 1, 2013

Filed:

Jan 29, 2010

Appl. No.:

12/697150

Inventors:

Richard S. Roy - Dublin CA, US
Dipak Kumar Sikdar - Santa Clara CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 8/00
G11C 8/16

US Classification:

36523003, 36523005

Abstract:

A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

US Patent:

20110197087, Aug 11, 2011

Filed:

Feb 9, 2010

Appl. No.:

12/702767

Inventors:

Dipak K. Sikdar - Santa Clara CA, US

International Classification:

G06F 1/08
G06F 12/00

US Classification:

713501, 713601, 711167, 711E12001

Abstract:

A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block.

US Patent:

20120250441, Oct 4, 2012

Filed:

Mar 31, 2011

Appl. No.:

13/077798

Inventors:

Richard S. Roy - Dublin CA, US
Dipak K. Sikdar - Santa Clara CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 7/12
G11C 7/06

US Classification:

365203, 365205

Abstract:

A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

US Patent:

20130003476, Jan 3, 2013

Filed:

Sep 10, 2012

Appl. No.:

13/609172

Inventors:

Dipak K. Sikdar - Santa Clara CA, US

Assignee:

MOSYS, INC. - Santa Clara CA

International Classification:

G11C 8/18

US Classification:

365194

Abstract:

A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal.

US Patent:

20130173970, Jul 4, 2013

Filed:

Jan 2, 2013

Appl. No.:

13/732783

Inventors:

Bendik Kleveland - Santa Clara CA, US
Dipak K. Sikdar - Santa Clara CA, US
Rajesh Chopra - San Ramon CA, US
Jay Patel - Los Gatos CA, US

Assignee:

MOSYS, INC. - Santa Clara CA

International Classification:

G11C 29/44

US Classification:

714710, 714718

Abstract:

A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

US Patent:

20130336074, Dec 19, 2013

Filed:

Aug 21, 2013

Appl. No.:

13/972798

Inventors:

Dipak Kumar Sikdar - Santa Clara CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

36518917

Abstract:

A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

US Patent:

20140082453, Mar 20, 2014

Filed:

Sep 18, 2013

Appl. No.:

14/031031

Inventors:

Dipak K. Sikdar - Santa Clara CA, US
Rajesh Chopra - San Ramon CA, US

Assignee:

MOSYS, INC. - Santa Clara CA

International Classification:

G06F 11/10

US Classification:

714763

Abstract:

An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.