Don B Lee

US Patent:

52456544, Sep 14, 1993

Filed:

Oct 10, 1991

Appl. No.:

7/775628

Inventors:

Dennis E. Wilkison - San Jose CA
Don N. Lee - San Jose CA

Assignee:

Cermetek Microelectronics, Inc. - Sunnyvale CA

International Classification:

H02H 322

US Classification:

379405

Abstract:

An isolation circuit (20) that is devoid of coupling transformers and yet suitable for use as a telephone line interface. The circuit is characterized by very wide bandwidth, low noise, and high linearity. Opto-isolators couple analog transmit and receive channels in a user device (12) across an isolation barrier (57) to a line pair for full duplex communication on the line pair. The interface circuit, which also includes a hybrid (55), includes first and second oppositely directed linear optocouplers (50,52). The first is disposed between the transmit channel and the hybrid; the second between the receive channel and the hybrid.

US Patent:

53572114, Oct 18, 1994

Filed:

May 3, 1993

Appl. No.:

8/056093

Inventors:

Stephen W. Bryson - Cupertino CA
Alan T. Kondo - Cupertino CA
Don N. Lee - San Jose CA

Assignee:

Raytheon Company - Lexington MA

International Classification:

H03F 326

US Classification:

330263

Abstract:

A pin driver amplifier having a complementary pair of transistors with a pair of resistors coupled between the respective emitters. A node between the resistors is coupled through an output series resistor to an output terminal adapted for connection of a transmission line that conducts driver pulses of predetermined voltage levels and timing to a device under test. A capacitor is tied between the emitters to provide a substantially constant reverse termination impedance for the transmission line thereby reducing reflections. Also, an RC network is coupled between the output terminal and ground to further reduce reflections. The amplifier transistors are driven by respective buffer transistor emitters that are tied together by a capacitor to make the positive and negative going drive capabilities for the amplifier transistors more equal. Further, capacitors are coupled between the amplifier collectors and ground to provide a bypass for parasitic inductance in the supply voltage wires.

US Patent:

53772024, Dec 27, 1994

Filed:

May 3, 1993

Appl. No.:

8/056097

Inventors:

Stephen W. Bryson - Cupertino CA
Alan T. Kondo - Cupertino CA
Don N. Lee - San Jose CA

Assignee:

Raytheon Company - Lexington MA

International Classification:

G05B 2302
G01R 1508

US Classification:

371 27

Abstract:

A test equipment pin driver having a main output channel including a pulse forming circuit, a buffer and an output amplifier connected in series. The pulse forming circuit provides pulses that are timed to a data input signal, and the buffer passes the pulses to the amplifier which produces driver pulses adapted to be transmitted to a device under test. The high and low voltage levels of the driver pulses are made substantially the same as programmed high and low voltages by providing scaled replicas of the buffer and amplifier, and using closed loop compensation to accurately drive the replica outputs to the high and low programmed voltages, respectively. The replicas mirror the DC performance of the buffer and amplifier of the main output channel, and clamping voltages are provided from the closed loops to enable operation of the main output channel in a manner that produces driver pulses with the programmed high and low voltage levels.

US Patent:

58421556, Nov 24, 1998

Filed:

May 3, 1993

Appl. No.:

8/056094

Inventors:

Stephen W. Bryson - Cupertino CA
Alan T. Kondo - Cupertino CA
Don N. Lee - San Jose CA

Assignee:

Fairchild Semiconductor Corp. - So. Portland ME

International Classification:

G01R 3102

US Classification:

702124

Abstract:

A method and apparatus for adjusting charging and discharging currents of a pin driver to optimize slew rates and overshoot for different types of logic circuits. The current charging and discharging circuits include respective transistors that are mirrored to a transistor whose current varies in accordance with VH-VL where VH and VL are programmed reference voltages defining the high and low voltage levels of the output driver pulses. Thus, when VH-VL is relatively large such as for CMOS outputs, slew rates are relatively high. However, when VH-VL is relatively small such as for ECL outputs, slew rates are reduced to prevent excessive overshoot.

US Patent:

20180205009, Jul 19, 2018

Filed:

Feb 28, 2017

Appl. No.:

15/445695

Inventors:

- Gyeonggi-do, KR
Dmytro Apalkov - San Jose CA, US
Vladimir Nikitin - Campbell CA, US
Don Koun Lee - San Jose CA, US

International Classification:

H01L 43/12
H01L 43/08
H01L 43/02
H01L 43/10
G11C 11/16

Abstract:

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. A first portion of a magnetoresistive stack corresponding to the magnetic junction is provided. Providing this portion of the magnetoresistive stack includes providing at least one layer for a free layer of the magnetic junction. A second portion of the magnetoresistive stack is provided after the step of providing the first portion of the magnetoresistive stack. The magnetoresistive stack is patterned to provide the magnetic junction after the step of providing the second portion of the magnetoresistive stack. An ambient temperature for the magnetoresistive stack and the magnetic junction does not exceed a crystallization temperature of the free layer after the step of providing the free layer through the step of patterning the magnetoresistive stack. The magnetic junction is annealed at an anneal temperature not less than the crystallization temperature after the step of patterning the magnetoresistive stack.

US Patent:

20170227598, Aug 10, 2017

Filed:

Feb 4, 2016

Appl. No.:

15/016151

Inventors:

- Tokyo, JP
Don LEE - San Jose CA, US
Roger MCALEENAN - San Jose CA, US
Kosuke MIYAO - San Jose CA, US

International Classification:

G01R 31/28
G01R 1/04

Abstract:

A structure for signal transmission is disclosed. The structure comprises a first plurality of waveguides tightly disposed together and disposed substantially in parallel with each other, each of said waveguides having a first opening and a second opening, wherein each first opening is operable to align with a patch antenna, and wherein the first plurality of waveguides is disposed adjacent to a socket. The integrated structure further comprises the socket which comprises an opening operable to support an insertion of a device under test (DUT), wherein the DUT is communicatively coupled to a plurality of microstrip transmission lines on a printed circuit board (PCB) underlying the socket for transmitting test signals from the DUT, wherein each of the microstrip transmission lines is electrically coupled to a respective patch antenna. Further, the first plurality of waveguides and the socket are integrated into a single plastic or metal structure.