Don Merrill Robinson

US Patent:

56969317, Dec 9, 1997

Filed:

Sep 9, 1994

Appl. No.:

8/303415

Inventors:

Marvin Mang-Yin Lum - San Jose CA
Don Michael Robinson - San Jose CA
Prafulla Bollampali Reddy - Santa Cruz CA
Kathleen Anne Duncan - Santa Cruz CA

Assignee:

Seagate Technology, Inc. - Scotts Valley CA

International Classification:

G06F 1208

US Classification:

395440

Abstract:

A disc controller services a host "read" command, without intervention by the disc controller's microcontroller, if the requested data is found in the disc controller's cache. The disc controller stores at least one cache entry. Each cache entry includes an address, a logical Bit, a valid Bit and a set of four buffer parameters: upper limit address, base address, pointer to the sector count and sector count. Each host command is decoded by the disc controller, and if the command is a "read" command the address in the cache entry is compared against the address in the host command. If the addresses match and the cache entry address is marked as being valid by its Valid bit, a "cache hit" signal is generated and the disc controller starts transferring the data requested by the host without waiting for the disc controller's microprocessor to process the host command. In particular, a sequencer and data transfer circuitry automatically generate a host interrupt request signal and transfer to the host at least a subset of the requested set of data blocks specified by each read command when a cache hit signal is generated. The disc controller includes circuitry for updating the information stored in the cache entry so that said updated information stored in the cache entry identifies data blocks in the cache sequentially subsequent to those data blocks transferred to the host.

US Patent:

45232750, Jun 11, 1985

Filed:

Mar 21, 1983

Appl. No.:

6/477563

Inventors:

Robert E. Swenson - Mendota Heights MN
Lawrence D. Sasscer - San Jose CA
Don M. Robinson - San Jose CA

Assignee:

Sperry Corporation - New York NY

International Classification:

G06F 1100
G06F 1300

US Classification:

364200

Abstract:

In a system having a host processor connected through a storage control unit to a cache store and a plurality of disk devices, segments of data which have been written to, while resident in the cache store, are transferred to the disks at some later time. If an abnormal condition, such as a bad spot on the disk, prevents the transfer of a segment from the cache store to the disk, an indicator is set for that segment by the storage control unit to prevent further attempts to transfer the segment. A segment whose indicator is set remains in the cache store until the host processor issues an initialize or a reset segment command.