Don L Simpson

US Patent:

20040124505, Jul 1, 2004

Filed:

Dec 27, 2002

Appl. No.:

10/331669

Inventors:

Richard Mahle - McKinney TX, US
Don Simpson - Sherman TX, US

International Classification:

H01L023/495

US Classification:

257/666000

Abstract:

Methods for manufacturing a semiconductor device package () with a leadframe () to plastic () mold lock are disclosed along with the associated package (). A method of the invention discloses manufacturing a packaged semiconductor device () using steps for forming a leadframe () with at least one borehole (). The borehole () region of the leadframe () is coined such that a lip () is formed at the junction of the borehole () and a leadframe () surface. Encapsulating the lip () with mold compound () forms a leadframe () to plastic () lock incorporated in the completed semiconductor device package ().

US Patent:

20090024324, Jan 22, 2009

Filed:

Jul 20, 2007

Appl. No.:

11/781110

Inventors:

Douglas W. Clark - McKinney TX, US
Nelson Kei Wai Leung - Plano TX, US
Don Lloyd Simpson - Sherman TX, US
Gary Glenn R. Dirige - Baguio City, PH
Martin Thomas Whitfield - Plano TX, US

International Classification:

G06F 19/00

US Classification:

702 1

Abstract:

A method and a system for automatically performing gauge repeatability and reproducibility (GRR) tests is provided. A handler is used to automatically move semiconductor devices from a device tray or other storage device into position for testing. When operating in a GRR mode, the handler is configured to place each of the semiconductor devices being tested in each possible testing position. A series of tests is performed on each of the semiconductor devices being tested in each of the possible testing positions. Furthermore, the series of tests may be repeated multiple times for each of the semiconductor devices in each position. In this embodiment, it is preferred that the semiconductor devices be reseated after each completing each series of tests. The semiconductor devices may be individual dies, systems on chips, multi-chip modules, or wafers.

US Patent:

60615079, May 9, 2000

Filed:

Dec 11, 1997

Appl. No.:

8/988580

Inventors:

Glenn R. Fitzgerald - Garland TX
Lowell Boggs - Lewisville TX
Amy Dessert - Plano TX
Michael Allen Walsh - Plano TX
Eric Gregory Moore - Richardson TX
Stephanie Luhring Smith - Plano TX
Don L. Simpson - Pottsboro TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3102

US Classification:

39550003

Abstract:

A method of using a processor-based integrated circuit (IC) tester (12) to automatically invoke diagnostic testing. A diagnostic schedule (30) is user-defined (FIG. 3), and checked by the tester (12) at various times, such as before and after the tester 12 tests an IC lot (FIGS. 6, 7, 8). The schedule (30) has various scheduling parameters that permit diagnostic testing to be scheduled to occur at certain times, at the expiration of intervals, or upon certain events. The schedule (30) also permits different levels of diagnostic testing, each level with its own schedule. The tester (12) is programmed to run an appropriate level of diagnostic testing if more than one level is due to occur.