Donald W Abbott

US Patent:

6683380, Jan 27, 2004

Filed:

Jul 10, 2002

Appl. No.:

10/191453

Inventors:

Taylor R. Efland - Richardson TX
Donald C. Abbott - Norton MA
Walter Bucksch - Freising, DE
Marco Corsi - Allen TX
John P. Erdeljac - Plano TX
Louis N. Hutter - Plano TX
Quang X. Mai - Sugarland TX
Konrad Wagensohner - Mauern, DE
Charles E. Williams - Dallas TX
Milton L. Buschbom - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257734, 438613

Abstract:

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

US Patent:

7217656, May 15, 2007

Filed:

May 31, 2005

Appl. No.:

11/140770

Inventors:

Howard R. Test - Plano TX, US
Donald C. Abbott - Norton MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438653, 438654, 438531, 438944, 257762, 257751

Abstract:

A metal structure for a contact pad of a wafer or substrate (), which have copper interconnecting traces () surrounded by a barrier metal layer (). The wafer or substrate is protected by an insulating overcoat (). In the structure, the barrier metal layer is selectively exposed by a window () in the insulating overcoat. A layer of copper (), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel () is adherent to the copper layer and a layer of noble metal () is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

US Patent:

7413974, Aug 19, 2008

Filed:

Aug 4, 2005

Appl. No.:

11/197002

Inventors:

Howard R. Test - Plano TX, US
Donald C. Abbott - Norton MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B32B 15/04
B32B 15/20
H01L 21/28
H01L 21/44

US Classification:

438614, 438612, 438618, 438652, 438687, 428610, 428620, 428670, 428672, 428673, 428674, 428680

Abstract:

A metal structure () for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer (). The substrate is protected by an insulating overcoat (). The first copper layer of first thickness and first crystallite size is selectively exposed by a window () in the insulating overcoat. A second copper layer () of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer () is on the second copper layer, and a noble metal layer () is on the nickel layer.

US Patent:

7535104, May 19, 2009

Filed:

Apr 11, 2007

Appl. No.:

11/733859

Inventors:

Howard R Test - Plano TX, US
Donald C Abbott - Norton MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48

US Classification:

257751, 257E29112, 257762, 257781, 438653, 438654, 438531, 438944

Abstract:

A metal structure for a contact pad of a wafer or substrate (), which have copper interconnecting traces () surrounded by a barrier metal layer (). The wafer or substrate is protected by an insulating overcoat (). In the structure, the barrier metal layer is selectively exposed by a window () in the insulating overcoat. A layer of copper (), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel () is adherent to the copper layer and a layer of noble metal () is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

US Patent:

7851928, Dec 14, 2010

Filed:

Jun 10, 2008

Appl. No.:

12/136231

Inventors:

Bernardo Gallegos - The Colony TX, US
Donald C. Abbott - Norton MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/52
H01L 23/48
H01L 29/40

US Classification:

257779, 257E23021, 257780, 257781, 257786, 438612

Abstract:

A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip with contact studs is attached onto the traces on tape. The traces, which are unprotected by soldermask , have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud is maximized. At the same time, the differential plating method of trace metal and through-hole metal allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.

US Patent:

20060125062, Jun 15, 2006

Filed:

Dec 15, 2004

Appl. No.:

11/015692

Inventors:

Edgar Zuniga-Ortiz - McKinney TX, US
Sreenivasan Koduri - Plano TX, US
Donald Abbott - Norton MA, US

International Classification:

H01L 23/495

US Classification:

257666000

Abstract:

A leadframe with a base metal structure (for example, copper) and first and second surfaces. A first metal layer, which is adhesive to polymeric materials such as molding compounds, is adherent to the first leadframe surface. The second leadframe surface is covered by a second metal layer for affinity to reflow metals such as tin alloy; this second metal layer has a different composition from the first metal layer. One example of the first surface is a nickel layer () in contact with the base metal (), a palladium layer () in contact with the nickel layer, and an outermost tin layer () in contact with the palladium. Another example is an oxidized surface of the base metal. The second metal layer, on the second leadframe surface, comprises a nickel layer () in contact with the base metal (), a palladium layer () in contact with the nickel layer, and an outermost gold layer () in contact with the palladium layer.

US Patent:

20080012101, Jan 17, 2008

Filed:

Sep 28, 2007

Appl. No.:

11/864233

Inventors:

Edgar Zuniga-Ortiz - McKinney TX, US
Sreenivasan Koduri - Plano TX, US
Donald Abbott - Norton MA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 23/495

US Classification:

257666000, 257E23031, 257E23054

Abstract:

A leadframe with a base metal structure (for example, copper) and first and second surfaces. A first metal layer, which is adhesive to polymeric materials such as molding compounds, is adherent to the first leadframe surface. The second leadframe surface is covered by a second metal layer for affinity to reflow metals such as tin alloy; this second metal layer has a different composition from the first metal layer. One example of the first surface is a nickel layer () in contact with the base metal (), a palladium layer () in contact with the nickel layer, and an outermost tin layer () in contact with the palladium. Another example is an oxidized surface of the base metal. The second metal layer, on the second leadframe surface, comprises a nickel layer () in contact with the base metal (), a palladium layer () in contact with the nickel layer, and an outermost gold layer () in contact with the palladium layer.

US Patent:

20080083993, Apr 10, 2008

Filed:

Jun 19, 2007

Appl. No.:

11/765286

Inventors:

Kejun Zeng - Coppell TX, US
Donald Abbott - Norton MA, US
Wei Qun Peng - Coppell TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 23/52
H01L 21/00

US Classification:

257777, 438125, 257E23141, 257E21001

Abstract:

A metal interconnection for two workplaces such as a semiconductor chip and an insulating substrate. The first workpiece () has a first contact pad () with a gold stud (); the second workplace () is covered with an insulating layer () and a window in the layer to a second contact pad (). The interconnection between the second pad and the gold stud is a 278 C. eutectic structure () with about 80 weight percent gold and about 20 weight percent tin. The eutectic structure has a Young's modulus of 59.2 GPa and a lamellar micro-structure of the phases AuSn and AuSn. There is substantially no metallic tin at the second contact pad.