Donald G Calhoun

US Patent:

43098118, Jan 12, 1982

Filed:

Jul 26, 1973

Appl. No.:

5/383020

Inventors:

Donald F. Calhoun - Torrance CA

Assignee:

Hughes Aircraft Company - Culver City CA

International Classification:

H01L 2116
H01L 21283

US Classification:

29574

Abstract:

A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usuable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master pattern mask common to the Y wafers and a plurality of other wafers to be connected into the specific circuit type.

US Patent:

42348889, Nov 18, 1980

Filed:

Jul 26, 1973

Appl. No.:

5/382993

Inventors:

Donald F. Calhoun - Inglewood CA
Barry Bennett - Wilmington CA

Assignee:

Hughes Aircraft Company - Culver City CA

International Classification:

H01L 2704

US Classification:

357 45

Abstract:

A complex integrated circuit comprising a wafer which has a plurality of cells each having signal-connect pads in a first layer of metalization on the wafer and which has an imperfect yield of usable cells. The circuit further includes a laminae of alternate layers of dielectric insulation and metalization formed on the wafer wherein: a first layer of insulation has vias formed therethrough to expose signal-connect pads of selected usable cells; a second layer of metalization has conductors formed therein which operably interconnect the exposed signal-connect pads of one or more groups of usable cells into individual functional circuits and, where needed, include pad relocation conductors which route the signal-connects of individual cells and the signal-connects of interconnected groups of cells to master pattern circuit locations; a second layer of insulation has vias formed therethrough which expose signal-connect portions at the master pattern circuit locations; and a third layer of metalization is formed into conductors that interconnect the signal-connects at master pattern locations into a functionally specified circuit type.

US Patent:

46315691, Dec 23, 1986

Filed:

Dec 13, 1974

Appl. No.:

5/532359

Inventors:

Donald F. Calhoun - Inglewood CA

Assignee:

Hughes Aircraft Company - El Segundo CA

International Classification:

H01L 2706

US Classification:

357 45

Abstract:

A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master pattern mask common to the Y wafers and a plurality of other wafers to be connected into the specific circuit type.