Donald Edward Collins

US Patent:

45134200, Apr 23, 1985

Filed:

Nov 22, 1982

Appl. No.:

6/443809

Inventors:

Donald A. Collins - Easley SC
Thomas B. O'Hanlan - Liberty SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1110

US Classification:

371 38

Abstract:

A method and apparatus for storing data in which the data is checked for an error without requiring the data to include an error correction code. Included in the system is a logic circuit for dividing a data word by a polynomial during the time the data word is being written into the primary memory unit resulting in the generation of a remainder which is stored in an auxiliary memory unit. When reading the data word from the primary memory unit, the data word is again divided by the same polynomial and the remainder compared with the remainder stored in the auxiliary memory unit. If the remainders match, no error was introduced during the storing of the data in the main memory unit. If the remainders do not match, an error is indicated. This system allows a data word to be stored in a main or primary memory unit without requiring the word to include error correction bytes.

US Patent:

45063656, Mar 19, 1985

Filed:

Nov 22, 1982

Appl. No.:

6/443835

Inventors:

Donald A. Collins - Easley SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1110

US Classification:

371 38

Abstract:

A method and apparatus for correcting single bit errors in data stored in a first memory includes a dynamic shift register for dividing data by a polynomial during the time the data is being written into the first memory resulting in the generation of a remainder which is stored in a second memory. When reading the data from the first memory, the data is again divided by the same polynomial. The remainder generated by the second division is compared with the remainder stored in the second memory. If the remainders do not match, indicating an error was introduced into the data during storage or retrieval of the data in the first memory, the remainder stored in the second memory is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data located in the second memory. As each zero bit is shifted into the shift register, a bit counter is incremented and the output bit of each stage of the shift register is examined. When the output of all the stages in the shift register except the last stage is zero and the last stage contains a binary bit one, the count of the bit counter points to the bit location in the data stored in the second memory locating the bit that is in error.