Donald L Draper

US Patent:

60965886, Aug 1, 2000

Filed:

Nov 1, 1997

Appl. No.:

8/969426

Inventors:

Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438197

Abstract:

A method of making an IGFET with a selected threshold voltage is disclosed. The method includes providing a semiconductor substrate with a device region that includes a source region, a drain region and a channel region therebetween, forming a gate over the channel region, introducing a threshold adjust dopant into the channel region after forming the gate without transferring essentially any of the threshold adjust dopant through the gate, thereby adjusting a threshold voltage of the IGFET, and forming a source in the source region and a drain in the drain region. Preferably, the threshold adjust dopant is introduced by implanting the threshold adjust dopant into the source region and diffusing the threshold adjust dopant from the source region into the channel region before providing any source/drain doping. The invention is well-suited for adjusting the threshold voltage, and therefore the drive current, leakage current and speed, of selected IGFETs, so that the fastest IGFETs with the highest leakage currents can be placed in critical speed paths such the tag to an instruction cache.

US Patent:

59259132, Jul 20, 1999

Filed:

Aug 25, 1997

Appl. No.:

8/918062

Inventors:

Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976
H01L 2994
H01L 31062
H01L 31113

US Classification:

257344

Abstract:

Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.

US Patent:

59990392, Dec 7, 1999

Filed:

Sep 26, 1997

Appl. No.:

8/938063

Inventors:

John Christian Holst - San Jose CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01J 1982

US Classification:

327532

Abstract:

An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

US Patent:

60339640, Mar 7, 2000

Filed:

Jul 2, 1998

Appl. No.:

9/109574

Inventors:

Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218228

US Classification:

438327

Abstract:

Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.

US Patent:

59594675, Sep 28, 1999

Filed:

Sep 26, 1997

Appl. No.:

8/938250

Inventors:

Joseph G. Nolan - San Jose CA
John C. Holst - San Jose CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line.

US Patent:

62850520, Sep 4, 2001

Filed:

Sep 26, 1997

Appl. No.:

8/939017

Inventors:

Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 27108
H01L 2976
H01L 2994
H01L 31119

US Classification:

257300

Abstract:

An integrated capacitor includes a device region of first conductivity type in a semiconductor substrate, a source/drain region of the first conductivity type in the device region with a higher doping concentration than the device region, a gate insulator over the device region, and a gate over the gate insulator. A first terminal is coupled to the source/drain region, and a second terminal is coupled to the gate. Advantageously, the integrated capacitor is operated with the device region beneath the gate driven into accumulation instead of inversion. This allows a lower voltage to be applied to the gate, which allows for a thinner gate insulator to be used resulting in higher capacitance per unit area. Furthermore, since the device region is much thicker and more highly conductive than an inversion layer, the integrated capacitor has greatly improved frequency response.

US Patent:

61278807, Oct 3, 2000

Filed:

Sep 7, 1999

Appl. No.:

9/391147

Inventors:

John Christian Holst - San Jose CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01J 1982

US Classification:

327531

Abstract:

An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.