Donald Royce Lang

US Patent:

48685143, Sep 19, 1989

Filed:

Nov 17, 1987

Appl. No.:

7/121667

Inventors:

Michael J. Azevedo - San Jose CA
Charles A. Corchero - Tucson AZ
Donald J. Lang - Cupertino CA
Gilbert R. Woodman - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 513
H03K 5159
H03K 1728
H03L 700

US Classification:

328155

Abstract:

This disclosure concerns digital correction of oscillator drift by providing phase alignment between two clock signals running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths of a variable delay path formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator. The product of phase comparison controls a digital delay selector to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signals. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal.

US Patent:

56424787, Jun 24, 1997

Filed:

Dec 29, 1994

Appl. No.:

8/366185

Inventors:

Chin-Huang Chen - San Jose CA
Mark C. Johnson - San Jose CA
Donald John Lang - Cupertino CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1108

US Classification:

39518321

Abstract:

A dedicated debugging facility for tracing hardware and software faults in a distributed digital system. An event data capture circuit is integrated into each processing node in a distributed multinode system for capturing event data within each node under software control. The captured event data is stored in one of a plurality of variable-length trace data buffers in the node processor memory space for analysis or transfer. These dedicated trace data acquisition circuits provide continuously available trace data for the hardware and software functions within each node. Each variable-length trace data entry is stored in the trace data buffers according to a format of this invention that permits collection and assembly of trace data entries from throughout the distributed multinode system to debug local hardware or software and to debug internodal interconnection hardware and software.

US Patent:

41033361, Jul 25, 1978

Filed:

Jul 26, 1976

Appl. No.:

5/708509

Inventors:

Abraham M. Gindi - San Jose CA
Donald John Lang - Cupertino CA

Assignee:

International Business Machines Incorporated - Armonk NY

International Classification:

G06F 300
G06F 900

US Classification:

364900

Abstract:

A loop system couples a CPU channel to bulk storage devices via a loop controller and device adapter. The loop system is characterized by equal fixed-length, multi-byte frames, each frame of which being assignable to only one terminal at a time. The system is further characterized by having a fixed loop delay greatly exceeding the frame duration by virtue of the high data rate. Dynamically variable frame assignment occurs when the primary terminal generates an unassigned empty frame in response to each assigned full (read) frame from a secondary terminal. The primary further generates an assigned full (write) frame upon receipt of each service (write) request frame from a secondary terminal. Lastly, the primary can send access command frames for each received unassigned empty frame or any other frame that does not imply a demand for bandwidth by the secondary. Relatedly, each secondary terminal can optionally write over a frame assigned to it or should it not have a message or data to send to the primary, change the "full" frame to "empty", or to seize an unassigned empty frame as it passes by on the loop.

US Patent:

50579975, Oct 15, 1991

Filed:

Feb 13, 1989

Appl. No.:

7/310409

Inventors:

Tai-Lin Chang - San Jose CA
Paul W. Hunter - San Jose CA
Donald J. Lang - Cupertino CA
Stephen G. Luning - San Jose CA

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 946

US Classification:

364200

Abstract:

In a programmed machine, such as an peripheral controller, programmed operations are executed in a one of several operational contexts. Each context may be initiated by a corresponding interruption signal. Any context which has been activated remains active until quiesced by program execution. One of the active contexts is a current context in which all instruction executions are currently occurring. In each cycle of the programmed machine, all active contexts and received and stored interruption signals, each for respective ones of the contexts, are compared to find the context highest priority context. Such highest priority context is compared with the current context priority for determining whether or not the programmed machine should change current contexts.

US Patent:

49691201, Nov 6, 1990

Filed:

Feb 13, 1989

Appl. No.:

7/310406

Inventors:

Michael J. Azevedo - San Jose CA
Paul W. Hunter - San Jose CA
Donald J. Lang - Cupertino CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

364900

Abstract:

An access control or arbitrator for a shared resource, such as a time-slotted bus, groups requests according to priorities of the requests. The time slots are grouped into sets, each set having a number of successive time slots equal to the number of sources supplying access requests having a highest priority. In a highest priority group, each source supplying a highest priority access request is guaranteed access in respective ones of said time slots in each set of time slots. When any time slot is not being used by a high priority request, low priority requests then have access to the unused time slot. Lower priority groups of access requests are handled in accordance with a different algorithm, such as a round robin priority algorithm.

US Patent:

56030444, Feb 11, 1997

Filed:

Feb 8, 1995

Appl. No.:

8/385761

Inventors:

Narasimhareddy L. Annapareddy - San Jose CA
Damon W. Finney - San Jose CA
Michael O. Jenkins - San Jose CA
Larry B. Kessler - San Jose CA
Donald J. Lang - Cupertino CA
Song C. Liang - San Jose CA
David N. Mora - San Jose CA
David A. Plomgren - San Carlos CA
Peter P. Urbisci - San Jose CA
Andrew D. Walls - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 902

US Classification:

395800

Abstract:

An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection.

US Patent:

58450726, Dec 1, 1998

Filed:

May 5, 1997

Appl. No.:

8/850284

Inventors:

Damon W. Finney - San Jose CA
Wen-Jei Ho - Saratoga CA
Mark C. Johnson - San Jose CA
Donald J. Lang - Cupertino CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520038

Abstract:

A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

US Patent:

57064431, Jan 6, 1998

Filed:

May 11, 1994

Appl. No.:

8/241904

Inventors:

James T. Brady - San Jose CA
Damon W. Finney - San Jose CA
Michael H. Hartung - Tucson AZ
Donald J. Lang - Cupertino CA
Jaishankar M. Menon - San Jose CA
David R. Nowlen - Morgan Hill CA
Calvin K. Tang - Saratoga CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

365250

Abstract:

A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.