Donald R Yu

US Patent:

6891394, May 10, 2005

Filed:

Jun 4, 2002

Appl. No.:

10/163096

Inventors:

Donald Y. Yu - Fremont CA, US
Wei-Min Kuo - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K019/173
H03H011/26

US Classification:

326 38, 326 47, 327278

Abstract:

A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

US Patent:

7119573, Oct 10, 2006

Filed:

May 5, 2005

Appl. No.:

11/123734

Inventors:

Donald Y. Yu - Fremont CA, US
Wei-Min Kuo - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/173
H03H 11/26

US Classification:

326 38, 326 47, 327278

Abstract:

A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

US Patent:

7378867, May 27, 2008

Filed:

Oct 10, 2006

Appl. No.:

11/548199

Inventors:

Donald Y. Yu - Fremont CA, US
Wei-Min Kuo - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

US Patent:

7434080, Oct 7, 2008

Filed:

Sep 3, 2002

Appl. No.:

10/235245

Inventors:

Wei-Min Kuo - San Jose CA, US
Donald Y. Yu - Fremont CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 1/04

US Classification:

713500, 713400, 713600

Abstract:

An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.

US Patent:

7545166, Jun 9, 2009

Filed:

Apr 25, 2008

Appl. No.:

12/109487

Inventors:

Donald Y. Yu - Fremont CA, US
Wei-Min Kuo - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 47

Abstract:

A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

US Patent:

7774665, Aug 10, 2010

Filed:

Aug 26, 2008

Appl. No.:

12/198249

Inventors:

Wei-Min Kuo - San Jose CA, US
Donald Y. Yu - Fremont CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G01R 31/28

US Classification:

714727, 714725, 714731

Abstract:

An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.

US Patent:

20050174095, Aug 11, 2005

Filed:

Feb 5, 2004

Appl. No.:

10/772714

Inventors:

Donald Yu - Anaheim CA, US

International Classification:

H02J001/00

US Classification:

320166000

Abstract:

A method for charge control of a photoflash capacitor. The method includes detecting a voltage on the photoflash capacitor, asserting and then latching a recharge signal when the detected voltage is lower than a first reference voltage, de-asserting and then latching the recharge signal when the detected voltage exceeds a second reference voltage, charging the photoflash capacitor when the recharge signal is asserted, and providing a pin for connection of a resistive element which determines the first reference voltage.

US Patent:

20050174096, Aug 11, 2005

Filed:

Feb 5, 2004

Appl. No.:

10/772728

Inventors:

Donald Yu - Anaheim CA, US

International Classification:

H02J001/00

US Classification:

320166000

Abstract:

A method for charge control of a photoflash capacitor. The method includes generating an input current to induce a charge current for the photoflash capacitor when an activation signal is asserted, detecting a first voltage from the photoflash capacitor and a second voltage corresponding to the input current, asserting and de-asserting a recharge signal respectively when the first detected voltage is lower and higher than a first reference voltage, asserting and de-asserting a current limit signal respectively when the second detected voltage is higher and lower than a second reference voltage, asserting the activation signal only when the recharge signal is asserted and the current limit signal is de-asserted, and providing a pin for connection of a resistive element which determines the second reference voltage.