Douglas M Armbrust

US Patent:

6512292, Jan 28, 2003

Filed:

Sep 12, 2000

Appl. No.:

09/660270

Inventors:

Douglas S. Armbrust - Gloucester MA
William F. Clark - Essex Junction VT
William A. Klaasen - Underhill VT
William T. Motsiff - Essex Junction VT
Timothy D. Sullivan - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2312

US Classification:

257712, 257347

Abstract:

Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.

US Patent:

6610607, Aug 26, 2003

Filed:

May 25, 2000

Appl. No.:

09/578362

Inventors:

Douglas S. Armbrust - Gloucester MA
Dale W. Martin - Hyde Park VT
Jed H. Rankin - Burlington VT
Sylvia Tousley - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21461

US Classification:

438717, 438671

Abstract:

A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.

US Patent:

6773952, Aug 10, 2004

Filed:

Sep 12, 2002

Appl. No.:

10/243397

Inventors:

Douglas S. Armbrust - Gloucester MA
William F. Clark - Essex Junction VT
William A. Klaasen - Underhill VT
William T. Motsiff - Essex Junction VT
Timothy D. Sullivan - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 54, 438 26, 438106

Abstract:

Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.

US Patent:

7094614, Aug 22, 2006

Filed:

Jan 16, 2001

Appl. No.:

09/681126

Inventors:

Douglas S. Armbrust - Gloucester MA, US
John M. Baker - Yorktown Heights NY, US
Arne W. Ballantine - Round Lake NY, US
Roger W. Cheek - Essex Junction VT, US
Doreen D. DiMilia - Pleasantville NY, US
Mark L. Reath - St. Albans VT, US
Michael B. Rice - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/66
B05C 11/00

US Classification:

438 14, 118712, 42725523

Abstract:

A method and apparatus are provided for controlling a CVD process used to deposit films on semiconductor substrates wherein the by-products of the reaction are measured and monitored during the reaction preferably using mass spectrometry and the results used to calculate the concentrations of the by-products and to control the CVD reaction process based on the by-product concentrations. An exemplary CVD process is the deposition of tungsten metal on a semiconductor wafer. A preferred method and apparatus uses a capillary gas sampling device for removing the by-product gases of the reaction as a feed for the mass spectrometer. The capillary gas sampling device is preferably connected to a differential pump.

US Patent:

20020145201, Oct 10, 2002

Filed:

Apr 4, 2001

Appl. No.:

09/681437

Inventors:

Douglas Armbrust - Stoneham MA, US
Jonathan Chapple-Sokol - Essex Junction VT, US
Anthony Stamper - Williston VT, US

International Classification:

H01L023/48

US Classification:

257/776000

Abstract:

A method and apparatus for creating air gaps to act as insulators within a semiconductor die. Wires, support structures, and sacrificial structures are constructed from vias and trenches. A top layer die is subdivided so that spaces reside between each adjacent subsection. The air gaps are created by etching the sacrificial structures via allowing etchant to seep through the spaces between subsections. After the air gaps have been created, the spaces residing between the subsections are sealed.