Douglas J Feist

US Patent:

7202656, Apr 10, 2007

Filed:

Feb 18, 2005

Appl. No.:

11/061292

Inventors:

Kevin Gearhardt - Fort Collins CO, US
Douglas Feist - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 23/12
G01R 23/175
G01R 13/02

US Classification:

324 7653, 324 7654, 324 7682

Abstract:

Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.

US Patent:

7240264, Jul 3, 2007

Filed:

Apr 28, 2005

Appl. No.:

11/116616

Inventors:

Kevin J. Gearhardt - Fort Collins CO, US
Douglas J. Feist - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/28

US Classification:

714726, 714734

Abstract:

An external scan test module that is adapted to act as an interface between an automated tester and a device under test. The external scan test module includes a scan pattern memory to hold scan patterns for at least one configuration of the device under test. A failure log memory holds failure information for the device under test. A controller sends scan input data to the device under test, receives scan output data from the device under test, and sends and receives signals from the automated tester. An interface receives scan patterns.

US Patent:

8619935, Dec 31, 2013

Filed:

Oct 26, 2010

Appl. No.:

12/912513

Inventors:

Douglas J. Feist - Fort Collins CO, US
Tracy J. Feist - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H04L 7/00
H03L 7/06
G06F 1/04

US Classification:

375371, 327158, 713503

Abstract:

Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

US Patent:

7081841, Jul 25, 2006

Filed:

Apr 28, 2005

Appl. No.:

11/117682

Inventors:

Douglas J. Feist - Fort Collins CO, US
Scott C. Savage - Ft. Collins CO, US
Kevin J. Gearhardt - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03M 1/20

US Classification:

341120, 341144, 341155

Abstract:

A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.