Douglas M Hendricks

US Patent:

51640228, Nov 17, 1992

Filed:

Feb 19, 1991

Appl. No.:

7/656385

Inventors:

Jerrold S. Pine - Boca Raton FL
Stefan Peana - Hollywood FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B23K 3534

US Classification:

148 23

Abstract:

In an apparatus for depositing flux onto a solder work surface, a chamber having a plurality of openings therein is heated by means of a U-shaped current conducting heating element within which the flux chamber resides. This heating element heats the flux within the chamber until it vaporizes and is forced from the chamber through the openings onto the solder work surface.

US Patent:

48892750, Dec 26, 1989

Filed:

Nov 2, 1988

Appl. No.:

7/266470

Inventors:

William B. Mullen - Boca Raton FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B23K 120
B23K 3100

US Classification:

2281802

Abstract:

A method for effecting high density solder interconnects between a substrate and at least one metalized film having through holes therein is provided. Solder is first applied to metalized portions of the substrates and the solder is then subject to a reflow process to provide reflowed solder. Pressure is applied to the reflowed solder during a second reflow process to provide prestressed or shaped solder. The metalized film is then positioned with at least one metalized portion adjacent to the shaped solder. Heat, as from a laser, is directed through the through holes in the film to melt the solder and form solder interconnections between the substrate and the metalized film.

US Patent:

57167605, Feb 10, 1998

Filed:

Mar 3, 1997

Appl. No.:

8/810272

Inventors:

Frank Juskey - Coral Springs FL
Jonathon G. Greenwood - Boynton Beach FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G03F 700

US Classification:

430315

Abstract:

A novel process for plating a substrate without solder mask wherein the substrate is coated with a polymer catalyst to assist adhesion of conductive metal to the substrate. Next, a first plating mask photopolymer, or plating resist, is coated over the polymer catalyst, a circuit pattern is imaged onto the first plating mask and the first plating mask is developed to reveal windows, or circuit traces, in the first plating mask corresponding to the circuit pattern to be embodied on the substrate. Thereafter, a first conductive material such as copper is plated into the windows, and, thereafter, a second conductive material such as nickel may be plated into the windows on top of the first conductive material. Then, the first plating mask is removed from the substrate, leaving behind the conductive material in the form of the desired circuit pattern. Next, a second plating mask photopolymer is formed over the substrate and conductive materials, and an I/O interconnect mask corresponding to the I/O interconnect pads is photo-optically imaged onto the second plating mask and the second plating mask is developed to remove portions thereof, creating "interconnect voids," corresponding to the interconnect pads.

US Patent:

53369319, Aug 9, 1994

Filed:

Sep 3, 1993

Appl. No.:

8/115971

Inventors:

Frank J. Juskey - Coral Springs FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2328
H01L 2329

US Classification:

257787

Abstract:

A flow formed encapsulated integrated circuit package (100) includes a printed circuit substrate (160) having upper and lower opposed surfaces and one or more anchor holes (150). The one or more anchor holes (150) have an upper aperture in the upper surface and a lower aperture in the lower surface. One or more integrated circuit die (130) are electrically and mechanically attached to the upper surface of the substrate (160). In addition, a solder resist mask (190) is attached to the lower surface of the substrate which covers the aperture of the one or more anchor holes (150). Flow formed material (110) is formed around the integrated circuit die (130) so as to encapsulate the one or more integrated circuits (150), the flow formed material (110) covering at a least a portion of the upper surface of the printed circuit substrate (160) and extending substantially into the anchor hole (150).

US Patent:

54391628, Aug 8, 1995

Filed:

Jun 28, 1993

Appl. No.:

8/082568

Inventors:

Reed A. George - Lake Worth FL
John P. Cheraso - Boynton Beach FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H05K 334

US Classification:

22818022

Abstract:

An integrated circuit (70) is soldered to a printed circuit board (200) by first depositing flux (116) on bumps (75) of the integrated circuit. Solder (214) is deposited upon the bumps (75), and the integrated circuits is (70) placed in contact with pads (210) on the printed circuit board (200). After reflow, a solder joint (230) electrically and mechanically attaches the integrated circuit (70) to the printed circuit board (200). Alternatively, the solder tipped (214) bumps (75) may be placed in contact with a non-adhering flat plane (300) such as glass during the heating process. After reflow, each bump has a flat portion (350), and the flat portions of all the bumps form a plane (400) which further facilitates attaching the integrated circuit (70) to the printed circuit board (200).

US Patent:

54360285, Jul 25, 1995

Filed:

Jul 27, 1992

Appl. No.:

7/918741

Inventors:

Christopher L. Becher - Boynton Beach FL
Richard L. Mangold - Boynton Beach FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B05D 100

US Classification:

427 96

Abstract:

A single screen printer (200) holds at least two solder stencils (225). The screen printer (200) receives a printed circuit board (105) and determines a printed circuit board configuration. When the printed circuit board (105) is of a first configuration, the printed circuit board (105) is aligned with a first stencil (225) and solder paste is selectively applied to the printed circuit board (105) through the first stencil (225). When the printed circuit board (105) is of a second configuration, the printed circuit board is aligned with a second stencil (225) through which solder paste is selectively applied to the printed circuit board (105).

US Patent:

56794983, Oct 21, 1997

Filed:

Oct 11, 1995

Appl. No.:

8/540873

Inventors:

Jonathon G. Greenwood - Boynton Beach FL
Douglas W. Hendricks - Boca Raton FL
Frank Juskey - Coral Springs FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G03F 738
G03F 740

US Classification:

430312

Abstract:

A method of producing multi-layered chip carriers by coating the surface of a base layer with a photosensitive dielectric material which forms a dielectric layer; curing at least a portion of the dielectric layer by exposure to radiation; depositing a catalyst on the cured portion of the dielectric layer to form a sensitized dielectric layer; applying a photoresist layer upon the sensitized dielectric layer; curing at least a portion of the photoresist layer; developing the cured photoresist layer by removing uncured portions, thereby exposing corresponding portions of the underlying sensitized dielectric layer; forming conductors on the exposed dielectric layer; stripping the cured photoresist layer: coating a layer of photosensitive dielectric material upon the cured dielectric layer; and repeating the steps to produce successive layers which form a multi-layer chip carrier having a plurality of conductor layers separated by layers of insulating dielectric material.

US Patent:

53239474, Jun 28, 1994

Filed:

May 3, 1993

Appl. No.:

8/055589

Inventors:

Frank Juskey - Coral Springs FL
Kenneth M. Wasko - Boca Raton FL
Douglas W. Hendricks - Boca Raton FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B23K 308

US Classification:

228 563

Abstract:

A method and apparatus for use in forming pre-positioned solder bumps (104) on a pad arrangement (100) of a substrate (101) include placing a predetermined pattern (306) of solder preforms (304) in contact with a meltable adhesive fluxing agent (302) on a carrier tape (402), and then heating the fluxing agent (302) to melt it. Next, the fluxing agent (302) is cooled to resolidify it, thereby securing the solder preforms (304) to the carrier tape (402). The carrier tape (402) is then aligned over the pad arrangement (100) and the solder preforms (304) are transferred to the pad arrangement (100) by heating the solder preforms (304) to form the solder bumps (104) in the predetermined pattern (306).